Pablo Saraza-Canflanca
Orcid: 0000-0003-2155-8305
According to our database1,
Pablo Saraza-Canflanca
authored at least 23 papers
between 2018 and 2024.
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Bibliography
2024
Statistical Characterization of Off-State Stress Degradation in Planar HKMG nFETs Using Device Arrays.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Exploiting Bias Temperature Instability for Reservoir Computing in Edge Artificial Intelligence Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Demonstration of Chip Overclock Detection by Employing Tamper-Aware Odometer Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
2023
A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array.
Proceedings of the 19th International Conference on Synthesis, 2023
Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices.
Proceedings of the 19th International Conference on Synthesis, 2023
Using dedicated device arrays for the characterization of TDDB in a scaled HK/MG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
On the Impact of the Biasing History on the Characterization of Random Telegraph Noise.
IEEE Trans. Instrum. Meas., 2022
Integr., 2022
A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation.
Proceedings of the 18th International Conference on Synthesis, 2022
A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
A Ring-Oscillator-Based Degradation Monitor Concept with Tamper Detection Capability.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2020
Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits.
IEEE Trans. Instrum. Meas., 2020
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level.
Integr., 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
2019
TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level.
Proceedings of the 16th International Conference on Synthesis, 2019
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models.
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 15th International Conference on Synthesis, 2018
A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation.
Proceedings of the 15th International Conference on Synthesis, 2018