Pablo Royer

According to our database1, Pablo Royer authored at least 6 papers between 2013 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Architecture, design and technology guidelines for crosspoint memories.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

2015
Real-time low-complexity automatic modulation classifier for pulsed radar signals.
IEEE Trans. Aerosp. Electron. Syst., 2015

Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

2013
A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013


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