Pablo Ibáñez

Carl Christian Kjelgaard Mikkelsen

Future Gener. Comput. Syst., 2024

2023

Accurate and efficient constrained molecular dynamics of polymers using Newton's method and special purpose code.

[BibT_eX]

[DOI]

Lorién López-Villellas

Juan José Galano-Frutos

Santiago Marco-Sola

Comput. Phys. Commun., July, 2023

BALANCER: bandwidth allocation and cache partitioning for multicore processors.

[BibT_eX]

[DOI]

J. Supercomput., June, 2023

Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor.

[BibT_eX]

[DOI]

Rubén Langarita

Adrià Armejach

IEEE ACM Trans. Comput. Biol. Bioinform., 2023

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

[BibT_eX]

[DOI]

Carlos Escuin

Fernando García-Redondo

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

RISC-V for Genome Data Analysis: Opportunities and Challenges.

[BibT_eX]

[DOI]

Lorién López-Villellas

Esteve Pineda-Sánchez

Asaf Badouh

Santiago Marco-Sola

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022

Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps.

[BibT_eX]

[DOI]

IEEE ACM Trans. Comput. Biol. Bioinform., 2022

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime.

[BibT_eX]

[DOI]

CoRR, 2022

Forecasting lifetime and performance of a novel NVM last-level cache with compression.

[BibT_eX]

[DOI]

CoRR, 2022

Berti: an Accurate Local-Delta Data Prefetcher.

[BibT_eX]

[DOI]

Biswabandan Panda

Alberto Ros

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches.

[BibT_eX]

[DOI]

Proceedings of the DroneSE and RAPIDO '22: System Engineering for constrained embedded systems, Budapest Hungary, January 17, 2022

2021

Near-optimal replacement policies for shared caches in multicore processors.

[BibT_eX]

[DOI]

J. Supercomput., 2021

A learning experience toward the understanding of abstraction-level interactions in parallel applications.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2021

Synchronization Strategies on Many-Core SMT Systems.

[BibT_eX]

[DOI]

Pablo Ibáñez-Marín

Maria Carpen-Amarie

Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

2020

Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor.

[BibT_eX]

[DOI]

Jose Manuel Herruzo

Sonia González-Navarro

Pablo Ibáñez-Marín

Alexandra Ferrerón-Labari

Oscar G. Plata

IEEE ACM Trans. Comput. Biol. Bioinform., 2020

2019

A fault-tolerant last level cache for CMPs operating at ultra-low voltage.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2019

ReD: A reuse detector for content selection in exclusive shared last-level caches.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2019

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.

[BibT_eX]

[DOI]

María Villarroya-Gaudó

Proceedings of the Workshop on Computer Architecture Education, 2019

Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.

[BibT_eX]

[DOI]

Jose Manuel Herruzo

Sonia González-Navarro

Víctor Viñals

Roberto Rodríguez-Rodríguez

Oscar G. Plata

Proceedings of the Data Compression Conference, 2019

2018

Reuse Detector: Improving the Management of STT-RAM SLLCs.

[BibT_eX]

[DOI]

Comput. J., 2018

2016

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage.

[BibT_eX]

[DOI]

Alexandra Ferrerón-Labari

Darío Suárez Gracia

Teresa Monreal Arnal

Carl Christian Kjelgaard Mikkelsen

IEEE Trans. Computers, 2016

2015

Accelerating Sparse Arithmetic in the Context of Newton's Method for Small Molecules with Bond Constraints.

[BibT_eX]

[DOI]

Agustín De Dios Hernández

Pablo Ibáñez-Marín

Pablo García-Risueño

Proceedings of the Parallel Processing and Applied Mathematics, 2015

2013

Exploiting reuse locality on inclusive shared last-level caches.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

The reuse cache: downsizing the shared last-level cache.

[BibT_eX]

[DOI]

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012

ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2012

Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers.

[BibT_eX]

[DOI]

Benjamín Sahelices

Agustín De Dios Hernández

José María Llabería

J. Comput. Sci. Technol., 2012

A review of High Performance Computing foundations for scientists

[BibT_eX]

[DOI]

Pablo García-Risueño

Pablo E. Ibáñez

CoRR, 2012

2011

Filtering directory lookups in CMPs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

Multi-level Adaptive Prefetching based on Performance Gradient Tracking.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2011

Filtering Directory Lookups in CMPs with Write-Through Caches.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2009

Store Buffer Design for Multibanked Data Caches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008

Low-Cost Adaptive Data Prefetching.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2008, 2008

2007

Data prefetching in a cache hierarchy with high bandwidth and capacity.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2007

Characterization of Apache web server with Specweb2005.

[BibT_eX]

[DOI]

Proceedings of the 2007 workshop on MEmory performance, 2007

2006

Software Demand, Hardware Supply.

[BibT_eX]

[DOI]

IEEE Micro, 2006

Speeding-Up Synchronizations in DSM Multiprocessors.

[BibT_eX]

[DOI]

Benjamín Sahelices Fernández

Víctor Viñals

José M. Llabería

Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

2005

Store Buffer Design in First-Level Multibanked Data Caches.

[BibT_eX]

[DOI]

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004

Contents Management in First-Level Multibanked Data Caches.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003

Counteracting Bank Misprediction in Sliced First-Level Caches.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2001

Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

2000

Modeling load address behaviour through recurrences.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

1998

Characterization and Improvement of Load/Store Cache-based Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 12th international conference on Supercomputing, 1998

1996

Performance Assessment of Contents Management in Multilevel On-Chip Caches.

[BibT_eX]

[DOI]