Pablo A. Ferreyra

According to our database, Pablo A. Ferreyra authored at least 10 papers between 2001 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Embedded wireless delay tolerant networks on chips for segmented architectures.

Pablo A. Ferreyra, Rubén Danilo Capkob, Alberto Fabián Gómez, Juan Andres Fraire, Carlos José Barrientos

Int. J. Embed. Syst., 2021

2019

A Wireless Embedded System for Measuring the Effects of Ionizing Radiations.

Daniel Sánchez, Pablo A. Ferreyra, Juan A. Fraire, Fabian Gomez, Raoul Velazco, Dardo Vinas Viscardi

Proceedings of the IEEE Latin American Test Symposium, 2019

Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results.

Pablo A. Ferreyra, Juan A. Fraire, Fabian Gomez, Raoul Velazco, Daniel Sánchez, Dardo Vinas Viscardi

Proceedings of the IEEE Latin American Test Symposium, 2019

2017

Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs.

M. Solinas, Alexandre Coelho, Juan A. Fraire, Nacer-Eddine Zergainoh, Pablo A. Ferreyra, Raoul Velazco

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

2016

Internetworking approaches towards along-track segmented satellite architectures.

Juan A. Fraire, Pablo G. Madoery, Jorge M. Finochietto, Pablo A. Ferreyra, Raoul Velazco

Proceedings of the 2016 IEEE International Conference on Wireless for Space and Extreme Environments, 2016

2009

Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications.

Ezequiel Brac, Pablo A. Ferreyra, Raoul Velazco, Carlos A. Marqués

Proceedings of the 10th Latin American Test Workshop, 2009

2004

Digital lock in amplifier: study, design and development with a digital signal processor.

Javier P. Gaspar, Suei Feng Chen, Alejandro Gordillo, Mateo Hepp, Pablo A. Ferreyra, Carlos A. Marqués

Microprocess. Microsystems, 2004

2002

SEU-Induced-Fault Detection-Efficiency of a Watch Dog Circuit for a Micro-Satellite on Board Digital Signal Processor System.

Pablo A. Ferreyra, Carlos A. Marqués, Javier P. Gaspar, Raul Velazco, Ricardo T. Ferreyra

Proceedings of the 3rd Latin American Test Workshop, 2002

Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied.

Raoul Velazco, A. Corominas, Pablo A. Ferreyra

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

A Software Tool for Simulating Single Event Upsets in a Digital Signal Processor.

Pablo A. Ferreyra, Carlos A. Marqués, Javier P. Gaspar, Ricardo T. Ferreyra

Proceedings of the 2nd Latin American Test Workshop, 2001