P. Veda Bhanu

Orcid: 0000-0001-5663-8407

According to our database1, P. Veda Bhanu authored at least 20 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2022
NoC Application Mapping Optimization Using Reinforcement Learning.
ACM Trans. Design Autom. Electr. Syst., 2022

Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation.
IEEE Access, 2022

2021
Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip.
J. Syst. Archit., 2021

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA.
IEEE Access, 2021

Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA.
IEEE Access, 2021

Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement.
ACM J. Emerg. Technol. Comput. Syst., 2019

Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimisation.
J. Exp. Theor. Artif. Intell., 2019

Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

FPGA Implementation of Novel Routing Algorithm for Butterfly-Fat-Tree Topology based NoC Design.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

A Link Fault Tolerant Routing Algorithm for Mesh of Tree Based Network-on-Chips.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization.
Proceedings of the 14th Conference on Industrial and Information Systems, 2019

2018
A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design.
Proceedings of the TENCON 2018, 2018

Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization.
Proceedings of the TENCON 2018, 2018

Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018


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