P. V. Sriniwas Shastry

According to our database, P. V. Sriniwas Shastry authored at least 2 papers between 2008 and 2012.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2012

Rolled architecture based implementation of AES using T-Box.

P. V. Sriniwas Shastry, Namrata Somani, Amruta Gadre, Bhagyashri Vispute, Mukul S. Sutaone

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2008

Low latency and high accuracy archtectures of cordic algorithm for cosine calculation on FPGA.

Gadgil Amruta, Parthe Yogita, Pathak Puja, P. V. Sriniwas Shastry

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008