P. Sivaranjani

Orcid: 0000-0002-5178-4613

According to our database1, P. Sivaranjani authored at least 8 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Design and Verification of Low Latency AMBA AXI4 and ACE Protocol for On-Chip Peripheral Communication.
Wirel. Pers. Commun., June, 2024

2023
Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis.
Wirel. Pers. Commun., March, 2023

PSO-DBNet for Peak-to-Average Power Ratio Reduction Using Deep Belief Network.
Comput. Syst. Sci. Eng., 2023

Design and Analysis of UART Protocol with Sec-Ded and Implementation on FPGA.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

Design of Arithmetic Logic Unit Using Hybrid Power Reduction Methodologies For Super Computer Applications.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

Verilog Implementation and Functional Verification of Hybrid Cryptography Algorithm.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2017
Hybrid Particle Swarm Optimization-Firefly algorithm (HPSOFF) for combinatorial optimization of non-slicing VLSI floorplanning.
J. Intell. Fuzzy Syst., 2017

2015
Thermal-Aware Non-slicing VLSI Floorplanning Using a Smart Decision-Making PSO-GA Based Hybrid Algorithm.
Circuits Syst. Signal Process., 2015


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