P. Saravanan

According to our database, P. Saravanan authored at least 21 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Low Cost Implementation of Authenticated Encryption Using Spongift.

R. Parthasarathy, P. Saravanan

Wirel. Pers. Commun., June, 2024

A Multiobjective Approach for Side-Channel Based Hardware Trojan Detection Using Power Traces.

Priyadharshini Mohanraj, Saravanan Paramasivam

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024

DEAC-IoT: Design of lightweight authenticated key agreement protocol for Intra and Inter-IoT device communication using ECC with FPGA implementation.

Mohammad Abdussami, Sanjeev Kumar Dwivedi, Taher Al-Shehari, P. Saravanan, Mohammed Kadrie, Taha Alfakih, Hussain Alsalman, Ruhul Amin

Comput. Electr. Eng., 2024

Three Stage Operational Amplifier with Split Length Differential Input Pair for IoT Applications.

P. Saravanan, Harreni V, Krishnaveni V

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

A Hardware Trojan Detection Method for Gate-Level Netlists Employing the CAMELOT Measure.

Priyadharshini Mohanraj, Saravanan Paramasivam, Charukesh V., Nihar Ahamed Fathima A.

Proceedings of the 7th International Conference on Devices, Circuits and Systems, 2024

2023

BSAPM: BlockChain based secured authentication protocol for large scale WSN with FPGA implementation.

Mohammad Abdussami, Ruhul Amin, P. Saravanan, Satyanarayana Vollala

Comput. Commun., September, 2023

Compact Quantum Circuit Design of PUFFIN and PRINT Lightweight Ciphers for Quantum Key Recovery Attack.

Saravanan Paramasivam, J. Jenitha, S. Sanjana, Majid Haghparast

IEEE Access, 2023

2022

Authenticated Key Agreement Protocol for Secure Communication Establishment in Vehicle-to-Grid Environment With FPGA Implementation.

Venkatasamy Sureshkumar, P. Chinnaraj, P. Saravanan, Ruhul Amin, Joel J. P. C. Rodrigues

IEEE Trans. Veh. Technol., 2022

2021

Time-shared AES-128 implementation with extremely low-cost for smart card applications.

P. Saravanan, Shanthi Rekha Shanmugham

Int. J. Inf. Comput. Secur., 2021

Hardware Accelerator for Dual Standard Deblocking Filter.

P. Saravanan, B. Syndia Priyadarshini, P. Vignesh Kanna, P. Vaishnavi

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Quantum Circuit Design of RECTANGLE Lightweight Cipher.

P. Saravanan, J. Jenitha, S. R. Aasish, S. Sanjana

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2019

Low-Cost AES-128 Implementation for Edge Devices in IoT Applications.

Shanthi Rekha Shanmugham, P. Saravanan

J. Circuits Syst. Comput., 2019

Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance.

S. Shanthi Rekha, P. Saravanan

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2018

Novel Reversible Design of Advanced Encryption Standard Cryptographic Algorithm for Wireless Sensor Networks.

P. Saravanan, P. Kalpana

Wirel. Pers. Commun., 2018

Survey on power analysis attacks and its impact on intelligent sensor networks.

Shanthi Rekha Shanmugham, Saravanan Paramasivam

IET Wirel. Sens. Syst., 2018

A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector Machine.

P. Saravanan, Babu M. Mehtre

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2017

Low Cost Circuit Level Implementation of PRESENT-80 S-BOX.

Shanthi Rekha Shanmugham, P. Saravanan

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2015

Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2^m) in Elliptic Curve Cryptography.

P. Saravanan, P. Kalpana

J. Circuits Syst. Comput., 2015

2014

Energy Efficient Reversible Building Blocks Resistant to Power Analysis Attacks.

P. Saravanan, P. Kalpana

J. Circuits Syst. Comput., 2014

Power analysis attack using neural networks with wavelet transform as pre-processor.

P. Saravanan, P. Kalpana, V. Prcethisri, V. Sneha

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2012

Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic.

P. Saravanan, P. Chandrasekar, Livya Chandran, Nikilla Sriram, P. Kalpana

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012