P. S. T. N. Srinivas

According to our database1, P. S. T. N. Srinivas authored at least 4 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Logic-in-memory application of silicon nanotube-based FBFET with core-source architecture.
Microelectron. J., 2024

2023
Impact of self-heating on thermal noise in In<sub>1-x</sub>Ga<sub>x</sub>As GAA MOSFETs.
Microelectron. J., 2023

Impact of Process-Induced Inclined Sidewalls On Small Signal Parameters of Silicon Nanowire GAA MOSFET.
Proceedings of the IEEE Region 10 Conference, 2023

2019
Analytical Modeling of Subthreshold Current and Subthreshold Swing of Schottky-Barrier Source/Drain Double Gate-All-Around (DGAA) MOSFETs.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019


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