P. Perreau
According to our database1,
P. Perreau
authored at least 5 papers
between 2009 and 2016.
Collaborative distances:
Collaborative distances:
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Bibliography
2016
Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2014
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2012
Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below.
Proceedings of the 35th European Solid-State Circuits Conference, 2009