P. Pant

According to our database, P. Pant authored at least 3 papers between 1998 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Innovative practices session 10C: Delay test.

P. Pant, M. Amodeo, Sujal Vora, Jonathon E. Colburn

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2001

Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits.

P. Pant, R. K. Roy, A. Chatterjee

IEEE Trans. Very Large Scale Integr. Syst., 2001

1998

Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits.

P. Pant, Vivek K. De, A. Chatterjee

IEEE Trans. Very Large Scale Integr. Syst., 1998