P. P. Chakrabarti

CoRR, 2021

Artificial Intelligence Methods Based Hierarchical Classification of Frontotemporal Dementia to Improve Diagnostic Predictability.

[BibT_eX]

[DOI]

Km Poonam

Rajlakshmi Guha

CoRR, 2021

City-scale Simulation of Covid-19 Pandemic and Intervention Policies using Agent-based Modelling.

[BibT_eX]

[DOI]

Gaurav Suryawanshi

Varun Madhavan

Adway Mitra

CoRR, 2021

City-Scale Simulation of Covid-19 Pandemic & Intervention Policies Using Agent-Based Modelling.

[BibT_eX]

[DOI]

Gaurav Suryawanshi

Varun Madhavan

Adway Mitra

Proceedings of the Winter Simulation Conference, 2021

2020

Early-Stage Resource Estimation from Functional Reliability Specification in Embedded Cyber-Physical Systems.

[BibT_eX]

[DOI]

Ginju V. George

Partha Pratim Chakraborty

CoRR, 2020

Antarjami: Exploring psychometric evaluation through a computer-based game.

[BibT_eX]

[DOI]

Proceedings of the 42th Annual Meeting of the Cognitive Science Society, 2020

'Eye Can Reason'- How Eye Parameters Marked one's Performance in a Visual Reasoning Task.

[BibT_eX]

[DOI]

Kaustav Brahma

Pourush Sood

Rajlakshmi Guha

Partha Pratim Chakraborty

Proceedings of the 42th Annual Meeting of the Cognitive Science Society, 2020

2019

Centralized Admissions for Engineering Colleges in India.

[BibT_eX]

[DOI]

Surender Baswana

Sharat Chandran

Yashodhan Kanoria

Utkarsh Patange

INFORMS J. Appl. Anal., 2019

Joint Seat Allocation 2018: An algorithmic perspective.

[BibT_eX]

[DOI]

CoRR, 2019

Factorization based dilution of biochemical fluids with micro-electrode-dot-array biochips.

[BibT_eX]

[DOI]

Sohini Saha

Debraj Kundu

Sukanta Bhattacharjee

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Demand-Driven Single- and Multitarget Mixture Preparation Using Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

2017

Fault Space Transformation: A Generic Approach to Counter Differential Fault Analysis and Differential Fault Intensity Analysis on AES-Like Block Ciphers.

[BibT_eX]

[DOI]

Sikhar Patranabis

Abhishek Chakraborty

Debdeep Mukhopadhyay

IEEE Trans. Inf. Forensics Secur., 2017

RELSPEC: a framework for reliability aware design of component based embedded systems.

[BibT_eX]

[DOI]

Saurav Kumar Ghosh

P. Vishnuvardhan

Soumyajit Dey

Des. Autom. Embed. Syst., 2017

Migration Aware Low Overhead ERfair Scheduler.

[BibT_eX]

[DOI]

Anshuman Tripathi

Piyoosh Purushothaman Nair

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016

ERfair Scheduler with Processor Suspension for Real-Time Multiprocessor Embedded Systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Anytime pack search.

[BibT_eX]

[DOI]

Nat. Comput., 2016

Formal assessment of reliability specifications in embedded cyber-physical systems.

[BibT_eX]

[DOI]

J. Appl. Log., 2016

2015

Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Waste-aware single-target dilution of a biochemical fluid using digital microfluidic biochips.

[BibT_eX]

[DOI]

Integr., 2015

Using State Space Encoding To Counter Biased Fault Attacks on AES Countermeasures.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Multi-mode Sampling Period Selection for Embedded Real Time Control.

[BibT_eX]

[DOI]

Rajorshee Raha

Soumyajit Dey

CoRR, 2015

Timing Analysis of Safety-Critical Automotive Software: The AUTOSAFE Tool Flow.

[BibT_eX]

[DOI]

Proceedings of the 2015 Asia-Pacific Software Engineering Conference, 2015

2014

Robustness Analysis of Embedded Control Systems with Respect to Signal Perturbations: Finding Minimal Counterexamples Using Fault Injection.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2014

Synthesis of sampling modes for adaptive control.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Control System, 2014

Demand-Driven Mixture Preparation and Droplet Streaming using Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Incremental Beam search.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2013

Formal Methods for Early Analysis of Functional Reliability in Component-Based Embedded Applications.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2013

Prediction Schemes for Compensating Variable Delay for Improving Performance of Real-Time Control Tasks.

[BibT_eX]

[DOI]

Saptarshi Roy

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Anytime Contract Search.

[BibT_eX]

[DOI]

Sunandita Patra

Proceedings of the Research and Development in Intelligent Systems XXX, 2013

Anytime Pack Heuristic Search.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition and Machine Intelligence, 2013

Ordered Solution Generation for Implicit AND/OR Search Spaces.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition and Machine Intelligence, 2013

Routing-aware resource allocation for mixture preparation in digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures : Extended Abstract.

[BibT_eX]

[DOI]

Amit Sharma

Proceedings of the IJCAI 2013, 2013

A Mobility Simulation Framework Of Humans With Group Behavior Modeling.

[BibT_eX]

[DOI]

Anshul Gupta

Aurosish Mishra

Tridib Mukherjee

Nathan Gnanasambandam

Proceedings of the 2013 IEEE 13th International Conference on Data Mining, 2013

Efficient mixture preparation on digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Handling fault detection latencies in automata-based scheduling for embedded control software.

[BibT_eX]

[DOI]

M. Santhosh Prabhu

Proceedings of the 2013 IEEE International Symposium on Computer-Aided Control System Design, 2013

2012

Online Scheduling of Dynamic Task Graphs with Communication and Contention for Multiprocessors.

[BibT_eX]

[DOI]

Pravanjan Choudhury

IEEE Trans. Parallel Distributed Syst., 2012

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

A dynamic assertion-based verification platform for validation of UML designs.

[BibT_eX]

[DOI]

P. Vignesh V. Ganesan

ACM SIGSOFT Softw. Eng. Notes, 2012

Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures.

[BibT_eX]

[DOI]

J. Artif. Intell. Res., 2012

SAT based timing analysis for fixed and rise/fall gate delay models.

[BibT_eX]

[DOI]

Integr., 2012

Cohesive Coverage Management: Simulation Meets Formal Methods.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Panel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere?

[BibT_eX]

[DOI]

Raju Bala Showry Pudota

Proceedings of the 25th International Conference on VLSI Design, 2012

Execution Ordering in AND/OR Graphs with Failure Probabilities.

[BibT_eX]

[DOI]

Proceedings of the Fifth Annual Symposium on Combinatorial Search, 2012

Algorithms for On-Chip Solution Preparation Using Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Finding Critical Components in Embedded Control Systems Sensitive to Quality-Faults.

[BibT_eX]

[DOI]

Vishal Shrivastav

Proceedings of the International Symposium on Electronic System Design, 2012

Anytime Algorithms for Mining Groups with Maximum Coverage.

[BibT_eX]

[DOI]

Proceedings of the Tenth Australasian Data Mining Conference, AusDM 2012, Sydney, 2012

Anytime Column Search.

[BibT_eX]

[DOI]

Piyush Gaurav

Proceedings of the AI 2012: Advances in Artificial Intelligence, 2012

Anytime Algorithms for Biobjective Heuristic Search.

[BibT_eX]

[DOI]

Proceedings of the AI 2012: Advances in Artificial Intelligence, 2012

2011

$\hbox {MAWA}^{\ast }$ - A Memory-Bounded Anytime Heuristic-Search Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Part B, 2011

A Corrigendum to: "Sticky-ERfair: a task-processor affinity aware proportional fair scheduler".

[BibT_eX]

[DOI]

Real Time Syst., 2011

Sticky-ERfair: a task-processor affinity aware proportional fair scheduler.

[BibT_eX]

[DOI]

Real Time Syst., 2011

A Low-Overhead Partition-Oriented ERfair Scheduler for Hard Real-Time Embedded Systems.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2011

Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Robust embedded software design through early analysis of quality faults.

[BibT_eX]

[DOI]

Proceedings of the Proceeding of the 4th Annual India Software Engineering Conference, 2011

A framework for early stage quality-fault tolerance analysis of embedded control systems.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011

2010

Thermal analysis of multiprocessor SoC applications by simulation and verification.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2010

Bounded delay timing analysis and power estimation using SAT.

[BibT_eX]

[DOI]

Microelectron. J., 2010

Partition oriented frame based fair scheduler.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2010

Heuristic search under contract.

[BibT_eX]

[DOI]

Comput. Intell., 2010

Safe-ERfair.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Accelerating Synchronous Sequential Circuits Using an Adaptive Clock.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Coverage Management with Inline Assertions and Formal Test Points.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

An analysis of breadth-first beam search using uniform cost trees.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Artificial Intelligence and Mathematics, 2010

Contract Search: Heuristic Search under Node Expansion Constraints.

[BibT_eX]

[DOI]

Proceedings of the ECAI 2010, 2010

2009

Design intent coverage revisited.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Scenario-based timing verification of multiprocessor embedded applications.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Adaptive parameter control of evolutionary algorithms to improve quality-time trade-off.

[BibT_eX]

[DOI]

Appl. Soft Comput., 2009

Inline Assertions - Embedding Formal Properties in a Test Bench.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

New Approaches to Design and Control of Time Limited Search Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition and Machine Intelligence, 2009

ERfair Scheduler with Processor Shutdown.

[BibT_eX]

[DOI]

Sarthak Swaroop

Proceedings of the 16th International Conference on High Performance Computing, 2009

2008

Satisfiability Models for Maximum Transition Power.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Hybrid Scheduling of Dynamic Task Graphs with Selective Duplication for Multiprocessors under Memory and Time Constraints.

[BibT_eX]

[DOI]

Pravanjan Choudhury

IEEE Trans. Parallel Distributed Syst., 2008

Simulation-based verification using Temporally Attributed Boolean Logic.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Auxiliary state machines + context-triggered properties in verification.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Cohesive Coverage Management for Simulation and Formal Property Verification.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Approaches to Design Intent Verification.

[BibT_eX]

[DOI]

Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

2007

Event propagation for accurate circuit delay calculation using SAT.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

A verification system for transient response of analog circuits.

[BibT_eX]

[DOI]

Tathagato Rai Dastidar

ACM Trans. Design Autom. Electr. Syst., 2007

Functional verification of task partitioning for multiprocessor embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

An Evolutionary Algorithm-Based Approach to Automated Design of Analog and RF Circuits Using Adaptive Normalized Cost Functions.

[BibT_eX]

[DOI]

IEEE Trans. Evol. Comput., 2007

An Automated Meta-Level Control Framework for Optimizing the Quality-Time Tradeoff of VLSI Algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

BUSpec: A framework for generation of verification aids for standard bus protocol specifications.

[BibT_eX]

[DOI]

Integr., 2007

Hardware accelerated constrained random test generation.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Statistical static timing analysis using symbolic event propagation.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2007

Bounded Delay Timing Analysis Using Boolean Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis.

[BibT_eX]

[DOI]

Sayak Ray

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors.

[BibT_eX]

[DOI]

Pravanjan Choudhury

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

AWA* - A Window Constrained Anytime Heuristic Search Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IJCAI 2007, 2007

Timing Analysis of Sequential Circuits Using Symbolic Event Propagation.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

2006

Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Design-Intent Coverage - A New Paradigm for Formal Property Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Frame-Based Proportional Round-Robin.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Instruction-Set-Extension Exploration Using Decomposable Heuristic Search.

[BibT_eX]

[DOI]

Samik Das

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A Framework for Estimating Peak Power in Gate-Level Circuits.

[BibT_eX]

[DOI]

Diganchal Chakraborty

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Formal methods for checking realizability of coalitions in 3-party systems.

[BibT_eX]

[DOI]

Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

A model-based hybrid evolutionary algorithm for fast yield-inclusive design space exploration of analog circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

SystemC Modeling and Validation of A RISC Processor System.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2006

Synthesis of system verilog assertions.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

What lies between design intent coverage and model checking?

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Discovering the input assumptions in specification refinement coverage.

[BibT_eX]

[DOI]

Prasenjit Basu

Sayantan Das

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Timing Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia-Pacific Software Engineering Conference (APSEC 2006), 2006

2005

A framework for systematic validation and debugging of pipeline simulators.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

A synthesis system for analog circuits based on evolutionary search and topological reuse.

[BibT_eX]

[DOI]

Tathagato Rai Dastidar

Partha Ray

IEEE Trans. Evol. Comput., 2005

Post-compilation optimization for multiple gains with pattern matching.

[BibT_eX]

[DOI]

ACM SIGPLAN Notices, 2005

A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Verification System for Transient Response of Analog Circuits Using Model Checking.

[BibT_eX]

[DOI]

Tathagato Rai Dastidar

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Dictionary Based Code Compression for Variable Length Instruction Encodings.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules.

[BibT_eX]

[DOI]

Prasenjit Basu

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Adaptive Control of Anytime Algorithm Parameters.

[BibT_eX]

Proceedings of the 2nd Indian International Conference on Artificial Intelligence, 2005

SAT based solutions for consistency problems in formal property specifications for open systems.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Multiobjective EA Approach for Improved Quality of Solutions for Spanning Tree Problem.

[BibT_eX]

[DOI]

Proceedings of the Evolutionary Multi-Criterion Optimization, 2005

Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

An Adaptive Framework for Solving Multiple Hard Problems Under Time Constraints.

[BibT_eX]

[DOI]

Proceedings of the Computational Intelligence and Security, International Conference, 2005

2004

The power of first-order quantification over states in branching and linear time temporal logics.

[BibT_eX]

[DOI]

Krishnendu Chatterjee

Inf. Process. Lett., 2004

Property Refinement Techniques for Enhancing Coverage of Formal Property Verification.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Formal Verification of Modules under Real Time Environment Constraints.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

The BUSpec platform for automated generation of verification aids for standard bus protocols.

[BibT_eX]

[DOI]

Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

Distributed Evolutionary Algorithm Search for Multiobjective Spanning Tree Problem.

[BibT_eX]

[DOI]

Proceedings of the Distributed Computing, 2004

Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures.

[BibT_eX]

[DOI]

Krishnendu Chatterjee

Proceedings of the Distributed Computing, 2004

Multiobjective Genetic Search for Spanning Tree Problem.

[BibT_eX]

[DOI]

Proceedings of the Neural Information Processing, 11th International Conference, 2004

Formal verification coverage: computing the coverage gap between temporal specifications.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Improved Quality of Solutions for Multiobjective Spanning Tree Problem Using Distributed Evolutionary Algorithm.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2004

A New Approach to Timing Analysis Using Event Propagation and Temporal Logic.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

A Branching Time Temporal Framework for Quantitative Reasoning.

[BibT_eX]

[DOI]

Krishnendu Chatterjee

J. Autom. Reason., 2003

Open computation tree logic with fairness.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Solving Constraint Optimization Problems from CLP-Style Specifications Using Heuristic Search Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Knowl. Data Eng., 2002

Quantified Computation Tree Logic.

[BibT_eX]

[DOI]

Anindya C. Patthak

Indrajit Bhattacharya

Anirban Dasgupta

Inf. Process. Lett., 2002

Open Computation Tree Logic for Formal Verification of Modules.

[BibT_eX]

[DOI]

Arindam Chakrabarti

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Timing analysis of tree-like RLC circuits.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Formal verification of module interfaces against real time specifications.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Min-max Computation Tree Logic.

[BibT_eX]

[DOI]

Jatindra Kumar Deka

Sriram Sankaranarayanan

Artif. Intell., 2001

Symbolic verification of Boolean constraints over partially specified functions.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Abstractions for model checking of event timings.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Abstraction of word-level linear arithmetic functions from bit-level component descriptions.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Model checking on timed-event structures.

[BibT_eX]

[DOI]

Jatindra Kumar Deka

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Solving multiple processor and multiple resource constrained scheduling problems using a genetic algorithm approach.

[BibT_eX]

[DOI]

S. A. Hussain

V. U. K. Sastry

Int. J. Comput. Math., 2000

1999

A design space exploration scheme for data-path synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

Partial Precedence Constrained Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays.

[BibT_eX]

[DOI]

Jatindra Kumar Deka

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams.

[BibT_eX]

[DOI]

Pankaj Chauhan

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Controlling State Explosion in Static Simulation by Selective Composition.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Multiobjective heuristic search - an introduction to intelligent search methods for multicriteria optimization.

[BibT_eX]

Computational intelligence, Vieweg, ISBN: 978-3-528-05708-4, 1999

1998

Complexity of Scheduling in High Level Synthesis.

[BibT_eX]

[DOI]

VLSI Design, 1998

Learning while solving problems in best first search.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Part A, 1998

A Framework for Learning in Search-Based Systems.

[BibT_eX]

[DOI]

IEEE Trans. Knowl. Data Eng., 1998

1997

Design Space Exploration for Data Path Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

EARTH: combined state assignment of PLA-based FSM's targeting area and testability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Multiobjektive Heuristic Search in AND/OR Graphs.

[BibT_eX]

[DOI]

J. Algorithms, 1996

Agent Search in Uniform b-Ary Trees: Multiple Goals and Unequal Costs.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1996

Searching Game Trees under a Partial Order.

[BibT_eX]

[DOI]

Artif. Intell., 1996

Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A New Competitive Algorithm for Agent Searching in Unknown Streets.

[BibT_eX]

[DOI]

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1996

1995

Utility of Pathmax in Partial Order Heuristic Search.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1995

A Correction to "Agent Searching in a Tree and the Optimality of Iterative Deepening".

[BibT_eX]

[DOI]

Artif. Intell., 1995

Combined optimization of area and testability during state assignment of PLA-based FSM's.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A Near Optimal Algorithm for the Extended Cow-Path Problem in the Presence of Relative Errors.

[BibT_eX]

[DOI]

Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1995

1994

Improving Greedy Algorithms by Lookahead-Search.

[BibT_eX]

[DOI]

J. Algorithms, 1994

Agent Searching in a Tree and the Optimality of Iterative Deepening.

[BibT_eX]

[DOI]

Artif. Intell., 1994

Algorithms for Searching Explicit AND/OR Graphs and their Applications to Problem Reduction Search.

[BibT_eX]

[DOI]

Artif. Intell., 1994

A New Approach to Synthesis of PLA-Based FSM's.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

Multiobjective Search in VLSI Design.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

A new approach for factorizing FSM's.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Combining State Assignment with PLA Folding.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1992

A General Best First Search Algorithm in AND/OR Graphs.

[BibT_eX]

[DOI]

J. Algorithms, 1992

Generalized best first search using single and multiple heuristics.

[BibT_eX]

[DOI]

Inf. Sci., 1992

A Simple 0.5-Bounded Greedy Algorithm for the 0/1 Knapsack Problem.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1992

Effective Use of Memory in Iterative Deepening Search.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1992

Qualitative Description of Three-Dimensional Scenes.

[BibT_eX]

[DOI]

Prabir K. Biswas

Jayanta Mukherjee

B. N. Chatterji

Int. J. Pattern Recognit. Artif. Intell., 1992

A New algorithm for combined PLA folding.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on VLSI Design, 1992

Interconnect Optimization Techniques in Data Path Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on VLSI Design, 1992

1991

Multiple Stack Branch and Bound.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1991

Reducing Reexpansions in Iterative-Deepening Search by Controlling Cutoff Bounds.

[BibT_eX]

[DOI]

Artif. Intell., 1991

1989

Increasing Search Efficiency Using Multiple Heuristics.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1989

Heuristic Search in Restricted Memory.

[BibT_eX]

[DOI]

Artif. Intell., 1989

Pruning by Upperbounds in Heuristic Search: Use of Approximate Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Knowledge Based Computer Systems, 1989

1988

Best first search in and/or graphs.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth ACM Annual Conference on Computer Science, 1988

1987

Distance functions in digital geometry.

[BibT_eX]

[DOI]

Partha Pratim Das

Biswanath N. Chatterji

Inf. Sci., 1987

Generalized distances in digital geometry.

[BibT_eX]

[DOI]

Partha Pratim Das

Biswanath N. Chatterji

Inf. Sci., 1987

Admissibility of A0* when Heuristics Overestimate.

[BibT_eX]

[DOI]

Artif. Intell., 1987

1986

Heuristic Search Through Islands.

[BibT_eX]

[DOI]