P. Karthigaikumar
Orcid: 0000-0003-4850-0090Affiliations:
- Karpagam College of Engineering, Coimbatore, India
- Karunya University, Coimbatore, India (former)
- Anna University, India (PhD 2011)
According to our database1,
P. Karthigaikumar
authored at least 34 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Proceedings of the 7th International Conference on Devices, Circuits and Systems, 2024
2023
Survey on Image Encryption Schemes, Bio cryptography and Efficient Encryption Algorithms.
Mob. Networks Appl., August, 2023
Wirel. Pers. Commun., 2023
2022
An Effective Software Based Method to Analyze SCA Countermeasures for Advanced Encryption Standard.
Wirel. Pers. Commun., 2022
2020
Neural Comput. Appl., 2020
Microprocess. Microsystems, 2020
Micro-machined silicon accelerometer with piezoresistive SCR implementation for glucolysis.
Int. J. Wavelets Multiresolution Inf. Process., 2020
2019
Implementation of Interior Noise Control System Using Digital Adaptive Filter for On-Road Car Applications.
Wirel. Pers. Commun., 2019
Meticulous fuzzy convolution C means for optimized big data analytics: adaptation towards deep learning.
Int. J. Mach. Learn. Cybern., 2019
An Optimized S-Box Circuit for High Speed AES Design with Enhanced PPRM Architecture to Secure Mammographic Images.
J. Medical Syst., 2019
FPGA implementation of modified error normalized LMS adaptive filter for ECG noise removal.
Clust. Comput., 2019
2018
A novel LMS algorithm for ECG signal preprocessing and KNN classifier based abnormality detection.
Multim. Tools Appl., 2018
FPGA implementation of an optimized key expansion module of AES algorithm for secure transmission of personal ECG signals.
Des. Autom. Embed. Syst., 2018
Mobile cloud computing for ECG telemonitoring and real-time coronary heart disease risk detection.
Biomed. Signal Process. Control., 2018
ECG Signal Preprocessing and SVM Classifier-Based Abnormality Detection in Remote Healthcare Applications.
IEEE Access, 2018
2017
Wirel. Pers. Commun., 2017
An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box.
Wirel. Pers. Commun., 2017
Neural Comput. Appl., 2017
Intell. Autom. Soft Comput., 2017
2016
Introduction to Special Issue 'Researches and Challenges in Green Radio Communication'.
Wirel. Pers. Commun., 2016
2015
Wirel. Pers. Commun., 2015
Int. J. Inf. Commun. Technol., 2015
2014
FPGA implementation of AES algorithm for high throughput using folded parallel architecture.
Secur. Commun. Networks, 2014
2013
Central Eur. J. Comput. Sci., 2013
2012
Smart Comput. Rev., 2012
2011
FPGA and ASIC implementation of robust invisible binary image watermarking algorithm using connectivity preserving criteria.
Microelectron. J., 2011
J. Syst. Archit., 2011
Low power implementation of audio watermarking using chirp spread spectrum technique.
Int. J. Inf. Comput. Secur., 2011
2010
Microelectron. J., 2010
Int. J. Image Graph., 2010
Hardware implementation of invisible image watermarking algorithm using secured binary image authentication technique.
Int. J. Electron. Secur. Digit. Forensics, 2010