P. Jaenen
According to our database1,
P. Jaenen
authored at least 2 papers
between 2005 and 2009.
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Bibliography
2009
Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2005
Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning development.
Microelectron. Reliab., 2005