P. Glenn Gulak
Affiliations:- University of Toronto, Canada
According to our database1,
P. Glenn Gulak
authored at least 96 papers
between 1986 and 2019.
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Bibliography
2019
Hardware-Based Linear Program Decoding With the Alternating Direction Method of Multipliers.
IEEE Trans. Signal Process., 2019
2018
A Multi-Gb/s Frame-Interleaved LDPC Decoder With Path-Unrolled Message Passing in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018
SecureMed: Secure Medical Computation Using GPU-Accelerated Homomorphic Encryption Scheme.
IEEE J. Biomed. Health Informatics, 2018
IEEE Trans. Biomed. Circuits Syst., 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Key Reconciliation with Low-Density Parity-Check Codes for Long-Distance Quantum Cryptography.
CoRR, 2017
Hardware-based linear programming decoding via the alternating direction method of multipliers.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
2016
IEEE Trans. Computers, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Fully Integrated On-Chip Coil in 0.13 µm CMOS for Wireless Power Transfer Through Biological Media.
IEEE Trans. Biomed. Circuits Syst., 2015
A CMOS sensor for rapid testing of pathogen susceptibility to pore-forming antibiotics.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
CMOS Tunable-Color Image Sensor With Dual-ADC Shot-Noise-Aware Dynamic Range Extension.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Biomed. Circuits Syst., 2013
IEEE Trans. Biomed. Circuits Syst., 2013
IEEE Trans. Biomed. Circuits Syst., 2013
Proceedings of the ESSCIRC 2013, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Biomed. Circuits Syst., 2012
Fully-integrated, power-efficient regulator and bandgap circuits for wireless-powered biomedical applications.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
2011
A robust RAM-THP architecture for downlink multiuser MISO transmission with user scheduling.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Performance analysis of lattice-reduction algorithms for a novel LR-compatible K-Best MIMO detector.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the Global Communications Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
VLSI implementation of a hardware-optimized lattice reduction algorithm for WiMAX/LTE MIMO detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
VLSI implementation of a WiMAX/LTE compliant low-complexity high-throughput soft-output K-Best MIMO detector.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Efficient Compensation of the Nonlinearity of Solid-State Power Amplifiers Using Adaptive Sequential Monte Carlo Methods.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
A systolic architecture of a Sequential Monte Carlo-based equalizer for frequency-selective MIMO channels.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
The application of lattice-reduction to the K-Best algorithm for near-optimal MIMO detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A pipelined scalable high-throughput implementation of a near-ML K-best complex lattice decoder.
Proceedings of the IEEE International Conference on Acoustics, 2008
2007
Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2007
A Preprocessing Method for PAPR Reduction in OFDM Systems by Modifying FFT and IFFT Matrices.
Proceedings of the IEEE 18th International Symposium on Personal, 2007
Application of Sequential Monte Carlo to M-QAM Schemes in the Presence of Nonlinear Solid-State Power Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Commun., 2006
An efficient architecture for distributed resampling for high-speed particle filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Papr Reduction in OFDM Systems Using Polynomial-Based Compressing and Iterative Expanding.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
2005
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders.
J. VLSI Signal Process., 2005
Proceedings of IEEE International Conference on Communications, 2005
2004
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004
2003
A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
In-building power lines as high-speed communication channels: channel characterization and a test channel ensemble.
Int. J. Commun. Syst., 2003
2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2000
Proc. IEEE, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
1999
Wirel. Pers. Commun., 1999
1998
A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Parallel structures for joint channel estimation and data detection over fading channels.
IEEE J. Sel. Areas Commun., 1998
J. Circuits Syst. Comput., 1998
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
1997
IEEE Trans. Commun., 1997
1996
Multicast contention resolution with single-cycle windowing using content addressable FIFO's.
IEEE/ACM Trans. Netw., 1996
Fully parallel integrated CAM/RAM using preclassification to enable large capacities.
IEEE J. Solid State Circuits, 1996
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996
1995
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995
1994
IEEE Trans. Commun., 1994
Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.
Inf. Process. Manag., 1994
A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits.
Proceedings of the Proceedings EURO-DAC'94, 1994
Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression.
Proceedings of the IEEE Data Compression Conference, 1994
1993
IEEE Trans. Signal Process., 1993
IEEE Trans. Commun., 1993
A Logic-enhanced Memory for Digital Data Recovery Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding.
Proceedings of the IEEE Data Compression Conference, 1993
1992
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
1991
Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up.
Proceedings of the 1991 International Conference on Acoustics, 1991
1988
IEEE J. Sel. Areas Commun., 1988
1987
IEEE Trans. Computers, 1987
1986
IEEE Trans. Computers, 1986
IEEE J. Sel. Areas Commun., 1986
IEEE J. Sel. Areas Commun., 1986