P. Conenna

According to our database, P. Conenna authored at least 2 papers between 2010 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology.

Giovanni Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, Andrea D'Alessandro, Luca De Santis, Domenico Di Cicco, W. Di Francesco, M. L. Gallese, Girolamo Gallo, Michele Incarnati, C. Lattaro, Agostino Macerola, G. G. Marotta, Violante Moschiano, D. Orlandi, F. Paolini, S. Perugini, Luigi Pilolli, P. Pistilli, G. Rizzo, F. Rori, Massimo Rossini, Giovanni Santin, Emanuele Sirizotti, A. Smaniotto, U. Siciliani, Marco Tiburzi, R. Meyer, A. Goda, B. Filipiak, Tommaso Vali, Mark Helm, Ramin Ghodsi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010

A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s.

G. G. Marotta, Agostino Macerola, Andrea D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, D. Rivers, Emanuele Sirizotti, F. Paolini, G. Imondi, G. Naso, Giovanni Santin, L. Botticchio, Luca De Santis, Luigi Pilolli, M. L. Gallese, Michele Incarnati, Marco Tiburzi, P. Conenna, S. Perugini, Violante Moschiano, W. Di Francesco, Matt Goldman, Chris Haid, Domenico Di Cicco, D. Orlandi, F. Rori, Massimo Rossini, Tommaso Vali, Ramin Ghodsi, Frank Roohparvar

Proceedings of the IEEE International Solid-State Circuits Conference, 2010