P. Balasubramanian

According to our database, P. Balasubramanian authored at least 53 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

A New Carry Look-Ahead Adder Architecture Enabling Improved Speed and Energy Efficiency.

Padmanabhan Balasubramanian, Douglas L. Maskell

Proceedings of the IEEE Pacific Rim Conference on Communications, 2024

2023

Fault-Tolerant Design Approach Based on Approximate Computing.

P. Balasubramanian, Douglas L. Maskell

CoRR, 2023

2022

Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits.

Padmanabhan Balasubramanian, Raunaq Nayar, Okkar Min, Douglas L. Maskell

Comput., 2022

2021

Gate-Level Static Approximate Adders.

P. Balasubramanian, Raunaq Nayar, Douglas L. Maskell

CoRR, 2021

An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application.

Padmanabhan Balasubramanian, Raunaq Nayar, Douglas L. Maskell, Nikos E. Mastorakis

IEEE Access, 2021

Image Compression using Approximate Addition.

Raunaq Nayar, Padmanabhan Balasubramanian, Douglas Leslie Maskell

Proceedings of the IEEE Region 10 Conference, 2021

A Boolean Heuristic for Disjoint SOP Synthesis.

Padmanabhan Balasubramanian, Anna Bernasconi, Valentina Ciriani, Tiziano Villa

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

An Approximate Adder with Reduced Error and Optimized Design Metrics.

Padmanabhan Balasubramanian, Raunaq Nayar, Douglas L. Maskell

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020

Quasi-Delay-Insensitive Implementation of Approximate Addition.

Padmanabhan Balasubramanian, Nikos E. Mastorakis

Symmetry, 2020

Hardware Optimized Approximate Adder with Normal Error Distribution.

Raunaq Nayar, Padmanabhan Balasubramanian, Douglas L. Maskell

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019

Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders.

P. Balasubramanian

CoRR, 2019

Indicating Asynchronous Array Multipliers.

P. Balasubramanian, Douglas L. Maskell

CoRR, 2019

Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder.

P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis

CoRR, 2019

Generalized Majority Voter Design Method for N-Modular Redundant Systems Used in Mission- and Safety-Critical Applications.

Jaytrilok Choudhary, P. Balasubramanian, Danny M. Varghese, Dhirendra Pratap Singh, Douglas L. Maskell

Comput., 2019

Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications.

P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis

Proceedings of the 3rd European Conference on Electrical Engineering and Computer Science, 2019

2018

Performance Comparison of some Synchronous Adders.

P. Balasubramanian

CoRR, 2018

Asynchronous Ripple Carry Adder based on Area Optimized Early Output Dual-Bit Full Adder.

P. Balasubramanian

CoRR, 2018

Approximate Early Output Asynchronous Adders Based on Dual-Rail Data Encoding and 4-Phase Return-to-Zero and Return-to-One Handshaking.

P. Balasubramanian

CoRR, 2018

A Self-Healing Redundancy Scheme for Mission/Safety-Critical Applications.

P. Balasubramanian, Douglas L. Maskell

IEEE Access, 2018

Hardware Efficient Approximate Adder Design.

P. Balasubramanian, Douglas L. Maskell

Proceedings of the TENCON 2018, 2018

A System Health Indicator for the Distributed Minority and Majority Voting Based Redundancy Scheme.

P. Balasubramanian, Douglas L. Maskell, Krishnamachar Prasad

Proceedings of the TENCON 2018, 2018

Majority and Minority Voted Redundancy for Safety-Critical Applications.

P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results.

P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Indicating Asynchronous Multipliers.

P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis

Proceedings of the 2nd European Conference on Electrical Engineering and Computer Science, 2018

2017

A Critique on "Asynchronous Logic Implementation Based on Factorized DIMS".

P. Balasubramanian

CoRR, 2017

Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis.

P. Balasubramanian, Cuong Dang, Douglas L. Maskell, K. Prasad

CoRR, 2017

Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic.

P. Balasubramanian, Cuong Dang, Douglas L. Maskell, K. Prasad

CoRR, 2017

Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding.

P. Balasubramanian, K. Prasad

CoRR, 2017

Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits.

P. Balasubramanian, R. T. Naayagi

CoRR, 2017

Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits.

P. Balasubramanian, R. T. Naayagi

CoRR, 2017

Asynchronous Early Output Dual-Bit Full Adders Based on Homogeneous and Heterogeneous Delay-Insensitive Data Encoding.

P. Balasubramanian, K. Prasad

CoRR, 2017

Approximate quasi-delay-insensitive asynchronous adders: Design and analysis.

P. Balasubramanian, Cuong Dang, Douglas L. Maskell

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A comparison of quasi-delay-insensitive asynchronous adder designs corresponding to return-to-zero and return-to-one handshaking.

P. Balasubramanian, Cuong Dang

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016

Comments on "Dual-rail asynchronous logic multi-level implementation".

P. Balasubramanian

Integr., 2016

FPGA Based Implementation of Distributed Minority and Majority Voting Based Redundancy for Mission and Safety-Critical Applications.

P. Balasubramanian, Nikos E. Mastorakis

CoRR, 2016

System Reliability, Fault Tolerance and Design Metrics Tradeoffs in the Distributed Minority and Majority Voting Based Redundancy Scheme.

P. Balasubramanian, Nikos E. Mastorakis

CoRR, 2016

Early Output Hybrid Input Encoded Asynchronous Full Adder and Relative-Timed Ripple Carry Adder.

P. Balasubramanian, K. Prasad

CoRR, 2016

Design of Synchronous Section-Carry Based Carry Lookahead Adders with Improved Figure of Merit.

P. Balasubramanian, Nikos E. Mastorakis

CoRR, 2016

A Fault Tolerance Improved Majority Voter for TMR System Architectures.

P. Balasubramanian, K. Prasad, Nikos E. Mastorakis

CoRR, 2016

An Asynchronous Early Output Full Adder and a Relative-Timed Ripple Carry Adder.

P. Balasubramanian, Nikos E. Mastorakis

CoRR, 2016

Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders.

P. Balasubramanian, Shigeru Yamashita

CoRR, 2016

Power, Delay and Area Comparisons of Majority Voters relevant to TMR Architectures.

P. Balasubramanian, Nikos E. Mastorakis

CoRR, 2016

Global versus Local Weak-Indication Self-Timed Function Blocks - A Comparative Analysis.

P. Balasubramanian, Nikos E. Mastorakis

CoRR, 2016

ASIC-based Implementation of Synchronous Section-Carry Based Carry Lookahead Adders.

P. Balasubramanian, Nikos E. Mastorakis

CoRR, 2016

2015

A distributed minority and majority voting based redundancy scheme.

P. Balasubramanian, Douglas L. Maskell

Microelectron. Reliab., 2015

2013

Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic.

P. Balasubramanian, David A. Edwards, William B. Toms

J. Circuits Syst. Comput., 2013

On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design.

P. Balasubramanian, Shigeru Yamashita

Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

2012

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders.

P. Balasubramanian, David A. Edwards, William B. Toms

VLSI Design, 2012

2010

Self-Timed Logic and the Design of Self-Timed Adders.

Padmanabhan Balasubramanian

PhD thesis, 2010

2009

Dual-Sum Single-Carry Self-Timed Adder Designs.

P. Balasubramanian, Doug A. Edwards

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Self-timed full adder designs based on hybrid input encoding.

P. Balasubramanian, David A. Edwards, Charlie Brej

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

Efficient Realization of Strongly Indicating Function Blocks.

P. Balasubramanian, David A. Edwards

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A New Design Technique for Weakly Indicating Function Blocks.

P. Balasubramanian, David A. Edwards

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008