Ozgur Sinanoglu

Proceedings of the IEEE International Test Conference, 2018

Customized locking of IP blocks on a multi-million-gate SoC.

[BibT_eX]

[DOI]

Abhrajit Sengupta

Mohammed Thari Nabeel

Mohammed Ashraf

Proceedings of the International Conference on Computer-Aided Design, 2018

Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Towards provably-secure performance locking.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Advancing hardware security using polymorphic and stochastic spin-hall effect devices.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Raise your game for split manufacturing: restoring the true functionality through BEOL.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Concerted wire lifting: Enabling secure and cost-effective split manufacturing.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2017

Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2017

Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2017

Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Adaptive Reduction of the Frequency Search Space for Multi-V<sub>dd</sub> Digital Circuits Using Variation Sensitive Ring Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration.

[BibT_eX]

[DOI]

Johann Knechtel

Ibrahim Abe M. Elfadel

Jens Lienig

Cliff C. N. Sze

IPSJ Trans. Syst. LSI Des. Methodol., 2017

A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Evolution of logic locking.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Rethinking split manufacturing: An information-theoretic approach with secure layout techniques.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

TTLock: Tenacious and traceless logic locking.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

What to Lock?: Functional and Parametric Locking.

[BibT_eX]

[DOI]

Abhrajit Sengupta

Benjamin Carrión Schäfer

Yiorgos Makris

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity.

[BibT_eX]

[DOI]

Johann Knechtel

Proceedings of the 54th Annual Design Automation Conference, 2017

Provably-Secure Logic Locking: From Theory To Practice.

[BibT_eX]

[DOI]

Abhrajit Sengupta

Mohammed Thari Nabeel

Mohammed Ashraf

Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

2016

Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Adapting to Varying Distribution of Unknown Response Bits.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Security Assessment of Cyberphysical Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE ACM Trans. Comput. Biol. Bioinform., 2016

On Improving the Security of Logic Locking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Comparative Security Analysis of Current and Emerging Technologies.

[BibT_eX]

[DOI]

IEEE Micro, 2016

Guest Editorial Special Issue on Secure and Trustworthy Computing.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

Security Analysis of Anti-SAT.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Supply-Chain Security of Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Computer, 2016

Thwarting timing attacks on NEMS relay based designs.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Power-side-channel analysis of carbon nanotube FET based design.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

CamoPerturb: secure IC camouflaging for minterm protection.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

SARLock: SAT attack resistant logic locking.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Do you trust your chip?

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Activation of logic encrypted chips: Pre-test or post-test?

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Microfluidic encryption of on-chip biochemical assays.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015

Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Belling the CAD: Toward Security-Centric Electronic System Design.

[BibT_eX]

[DOI]

Aman Ali

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Guest Editorial Special Section on Hardware Security and Trust.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Fault Analysis-Based Logic Encryption.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

MAGIC: Malicious Aging in Circuits/Cores.

[BibT_eX]

[DOI]

Naghmeh Karimi

Arun Karthik Kanuparthi

Xueyang Wang

ACM Trans. Archit. Code Optim., 2015

TMO: A new class of attack on cipher misusing test infrastructure.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Timing attack on NEMS relay based design of AES.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A secure design-for-test infrastructure for lifetime security of SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Power analysis attacks on ARX: An application to Salsa20.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Transforming between logic locking and IC camouflaging.

[BibT_eX]

[DOI]

Proceedings of the 10th International Design & Test Symposium, 2015

Security implications of cyberphysical digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Security analysis of logic encryption against the most effective side-channel attack: DPA.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Scan attack on Elliptic Curve Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Regaining Trust in VLSI Design: Design-for-Trust Techniques.

[BibT_eX]

[DOI]

Proc. IEEE, 2014

Detection, diagnosis, and repair of faults in memristor-based memories.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

AES design space exploration new line for scan attack resiliency.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Test-mode-only scan attack and countermeasure for contemporary scan architectures.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

New scan attacks against state-of-the-art countermeasures and DFT.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Test-mode-only scan attack using the boundary scan chain.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Slack removal for enhanced reliability and trust.

[BibT_eX]

[DOI]

Abishek Ramdas

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Approximating the age of RF/analog circuits through re-characterization and statistical estimation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Secure Memristor-based Main Memory.

[BibT_eX]

[DOI]

Naghmeh Karimi

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Predictive Techniques for Projecting Test Data Volume Compression.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Scan to Nonscan Conversion via Test Cube Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Testing Chips With Spare Identical Cores.

[BibT_eX]

[DOI]

Abishek Ramdas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Eliminating the Timing Penalty of Scan.

[BibT_eX]

[DOI]

Vishwani D. Agrawal

J. Electron. Test., 2013

Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints.

[BibT_eX]

[DOI]

Sara Bunian

J. Electron. Test., 2013

Expedited-compact architecture for average scan power reduction.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

Sneak-path Testing of Memristor-based Memories.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

New scan-based attack using only the test mode.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Embedded tutorial: Regaining hardware security and trust.

[BibT_eX]

[DOI]

Proceedings of the 14th Latin American Test Workshop, 2013

VLSI testing based security metric for IC camouflaging.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

High-level synthesis for security and trust.

[BibT_eX]

[DOI]

Huan Zhang

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Scan attack in presence of mode-reset countermeasure.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Sneak path testing and fault modeling for multilevel memristor-based memories.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Reconciling the IC test and security dichotomy.

[BibT_eX]

[DOI]

Naghmeh Karimi

Proceedings of the 18th IEEE European Test Symposium, 2013

Adaptive reduction of the frequency search space for multi-vdd digital circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Is split manufacturing secure?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Security analysis of integrated circuit camouflaging.

[BibT_eX]

[DOI]

Michael Sam

Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

2012

Multi-modal response compaction adaptive to x-density variation.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2012

Fault Model Independent, Maximal Compaction of Test Responses in the Presence of Unknown Response Bits.

[BibT_eX]

[DOI]

Comput. J., 2012

An Optimal Inherently Stabilizing 2-Neighborhood Crash Resilient Protocol for Secure and Reliable Routing in Hypercube Networks.

[BibT_eX]

[DOI]

Mehmet Hakan Karaata

Bader F. AlBdaiwi

Comput. J., 2012

Eliminating Performance Penalty of Scan.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

Retiming scan circuit to eliminate timing penalty.

[BibT_eX]

[DOI]

Vishwani D. Agrawal

Proceedings of the 13th Latin American Test Workshop, 2012

Test access mechanism for chips with spare identical cores.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Engineering crossbar based emerging memory technologies.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Adaptive testing: Conquering process variations.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

Adaptive testing of chips with varying distributions of unknown response bits.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

DfT support for launch and capture power reduction in launch-off-capture testing.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

Toggle-masking scheme for x-filtering.

[BibT_eX]

[DOI]

Abishek Ramdas

Proceedings of the 17th IEEE European Test Symposium, 2012

Logic encryption: A fault analysis perspective.

[BibT_eX]

[DOI]

Youngok K. Pino

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Security analysis of logic obfuscation.

[BibT_eX]

[DOI]

Youngok K. Pino

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Unified 2-D X-Alignment for Improving the Observability of Response Compactors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits.

[BibT_eX]

[DOI]

Eman AlQuraishi

J. Low Power Electron., 2011

Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2011

Enhancing encoding capacity of combinational test stimulus decompressors.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2011

Expedited response compaction for scan power reduction.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Design and analysis of ring oscillator based Design-for-Trust technique.

[BibT_eX]

[DOI]

Vinayaka Jyothi

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Revival of partial scan: Test cube analysis driven conversion of flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Error-resilient design of branch predictors for effective yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

Toggle-Based Masking Scheme for Clustered Unknown Response Bits.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

An Inherently Stabilizing Algorithm for Node-To-Node Routing over All Shortest Node-Disjoint Paths in Hypercube Networks.

[BibT_eX]

[DOI]

Mehmet Hakan Karaata

Bader F. AlBdaiwi

IEEE Trans. Computers, 2010

On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power.

[BibT_eX]

[DOI]

Shouq Alsubaihi

J. Electron. Test., 2010

Predictive analysis for projecting test compression levels.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG.

[BibT_eX]

[DOI]

Proceedings of the 5th International Design and Test Workshop, 2010

Reconfigurable low-power Concurrent Error Detection in logic circuits.

[BibT_eX]

[DOI]

Sara Bunian

Proceedings of the 5th International Design and Test Workshop, 2010

Add-on blocks and algorithms for improving stimulus compression.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

XOR-Based Response Compactor Adaptive to X-Density Variation.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Pattern Encodability Enhancements for Test Stimulus Decompressors.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Scan Chain Hold-Time Violations: Can They be Tolerated?

[BibT_eX]

[DOI]

Philip Schremmer

IEEE Trans. Very Large Scale Integr. Syst., 2009

X-Align: Improving the Scan Cell Observability of Response Compactors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Align-Encode Delay Assignment in the Case of XOR-Decompressors: Impact of Parallel Computations.

[BibT_eX]

[DOI]

J. Interconnect. Networks, 2009

Scan Cell Positioning for Boosting the Compression of Fan-Out Networks.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2009

Utilisation of inverse compatibility for test cost reductions.

[BibT_eX]

[DOI]

Mohammed Nael Taha

IET Comput. Digit. Tech., 2009

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

X-alignment techniques for improving the observability of response compactors.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Isolation Techniques for Soft Cores.

[BibT_eX]

[DOI]

Tsvetomir Petrov

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Scan Architecture With Align-Encode.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Construction of an adaptive scan network for test time and data volume reduction.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Peak Power Reduction Through Dynamic Partitioning of Scan Chains.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing.

[BibT_eX]

[DOI]

Erik Jan Marinissen

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Low Cost Scan Test by Test Correlation Utilization.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2007

Diagnosis, modeling and tolerance of scan chain hold-time violations.

[BibT_eX]

[DOI]

Philip Schremmer

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A non-intrusive isolation approach for soft cores.

[BibT_eX]

[DOI]

Tsvetomir Petrov

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005

Test power reductions through computationally efficient, decoupled scan chain modifications.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2005

Efficient RT-Level Fault Diagnosis.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

2004

Fast and energy-frugal deterministic test through efficient compression and compaction techniques.

[BibT_eX]

[DOI]

J. Syst. Archit., 2004

Autonomous Yet Deterministic Test of SOC Cores.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Extending the Applicability of Parallel-Serial Scan Designs.

[BibT_eX]

[DOI]

Baris Arslan

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Pipelined test of SOC cores through test data transformations.

[BibT_eX]

[DOI]

Proceedings of the 9th European Test Symposium, 2004

Scan Power Minimization through Stimulus and Response Transformations.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Efficient RT-level fault diagnosis methodology.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Reducing Average and Peak Test Power Through Scan Chain Modification.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Compacting Test Responses for Deeply Embedded SoC Cores.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

Modeling Scan Chain Modifications For Scan-in Test Power Minimization.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Aggressive Test Power Reduction Through Test Stimuli Transformation.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Partial Core Encryption for Performance-Efficient Test of SOCs.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Parity-based output compaction for core-based SOCs [logic testing].

[BibT_eX]

[DOI]

Proceedings of the 8th European Test Workshop, 2003

Hierarchical Constraint Conscious RT-level Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Efficient Construction of Aliasing-Free Compaction Circuitry.

[BibT_eX]

[DOI]

IEEE Micro, 2002

Test Power Reduction through Minimization of Scan Chain Transitions.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Scan Power Reduction Through Test Data Transition Frequency Analysis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A novel scan architecture for power-efficient, rapid test.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Dynamic test data transformations for average and peak power reductions.

[BibT_eX]

[DOI]

Proceedings of the 7th European Test Workshop, 2002

Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

RT-level Fault Simulation Based on Symbolic Propagation.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Space and time compaction schemes for embedded cores.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Compaction Schemes with Minimum Test Application Time.

[BibT_eX]

[DOI]