Osnat Keren

Orcid: 0000-0002-3101-9551

According to our database1, Osnat Keren authored at least 78 papers between 1997 and 2024.

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Bibliography

2024
On Codes for Detecting Address and Data Manipulations in Memory Arrays.
IEEE Trans. Inf. Theory, August, 2024

Consolidated Linear Masking (CLM): Generalized Randomized Isomorphic Representations, Powerful Degrees of Freedom and Low(er)-cost.
IACR Cryptol. ePrint Arch., 2024

STORM - Small Table Oriented Redundancy-based SCA Mitigation for AES.
IACR Cryptol. ePrint Arch., 2024

Refinement and Empirical Side-Channel Analysis of Inner Product Masking with Robust Error Detection.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

Hardening Bus-Encoders with Power-Aware Single Error Correcting Codes.
Proceedings of the IEEE European Test Symposium, 2024

2023
Silicon Proven 1.29 μm × 1.8 μm 65nm Sub-Vt Optical Sensor for Hardware Security Applications.
IEEE Access, 2023

2022
Nonlinear Code-Based Low-Overhead Fine-Grained Control Flow Checking.
IEEE Trans. Computers, 2022

2021
Protecting Multi-Level Memories From Jamming Using Q-ary Expurgated Robust Codes.
IEEE Trans. Dependable Secur. Comput., 2021

IPM-RED: combining higher-order masking with robust error detection.
J. Cryptogr. Eng., 2021

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads.
IEEE Access, 2021

Compact Protection Codes for protecting memory from malicious data and address manipulations.
Proceedings of the 26th IEEE European Test Symposium, 2021

On resilience of security-oriented error detecting architectures against power attacks: a theoretical analysis.
Proceedings of the CF '21: Computing Frontiers Conference, 2021

2020
Constructive Bounds on the Capacity of Parallel Asynchronous Skew-Free Channels With Glitches.
IEEE Trans. Inf. Theory, 2020

An SRAM-Based PUF With a Capacitive Digital Preselection for a 1E-9 Key Error Probability.
IEEE Trans. Circuits Syst., 2020

On the Existence of Security Enhancing Converter Designs for Multi-Level Memories.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Error control scheme for malicious and natural faults in cryptographic modules.
J. Cryptogr. Eng., 2020

A Method to Utilize Mismatch Size to Produce an Additional Stable Bit in a Tilting SRAM-Based PUF.
IEEE Access, 2020

Temporal Power Redistribution as a Countermeasure against Side-Channel Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Nonlinear Codes for Control Flow Checking.
Proceedings of the IEEE European Test Symposium, 2020

2019
High Rate Robust Codes with Low Implementation Complexity.
IEEE Trans. Dependable Secur. Comput., 2019

Silicon Proven 1.8 µm × 9.2 µm 65-nm Digital Bit Generator for Hardware Security Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 7T Security Oriented SRAM Bitcell.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Toward Error-Correcting Architectures for Cryptographic Circuits Based on Rabii-Keren Codes.
IEEE Embed. Syst. Lett., 2019

A new class of security oriented error correcting robust codes.
Cryptogr. Commun., 2019

A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives.
Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019

Compact Sub-Vt Optical Sensor for the Detection of Fault Injection in Hardware Security Applications.
Proceedings of the 10th IFIP International Conference on New Technologies, 2019

FPGA Implementation of pAsynch Design Paradigm.
Proceedings of the 10th IFIP International Conference on New Technologies, 2019

On the Reliability of the Ring Oscillator Physically Unclonable Functions.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

Nonlinear Product Codes for Reliability and Security.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A Highly Reliable SRAM PUF with a Capacitive Preselection Mechanism and pre-ECC BER of 7.4E-10.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Security-oriented Code-based Architectures for Mitigating Fault Attacks.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Embedded randomness and data dependencies design paradigm: Advantages and challenges.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Detection and Correction of Malicious and Natural Faults in Cryptographic Modules.
Proceedings of the PROOFS 2018, 2018

Utilization of Process and Supply Voltage Random Variations for Random Bit Generation.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
CPA Secured Data-Dependent Delay-Assignment Methodology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Reliable Communications Across Parallel Asynchronous Channels With Arbitrary Skews.
IEEE Trans. Inf. Theory, 2017

A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits.
IEEE Access, 2017

Jamming resistant encoding for non-uniformly distributed information.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

A New Construction of Minimum Distance Robust Codes.
Proceedings of the Coding Theory and Applications - 5th International Castle Meeting, 2017

Reliable Communication Across Parallel Asynchronous Channels with Glitches.
Proceedings of the Coding Theory and Applications - 5th International Castle Meeting, 2017

Vulnerability of secured IoT memory against localized back side laser fault injection.
Proceedings of the Seventh International Conference on Emerging Security Technologies, 2017

2016
CMOS Based Gates for Blurring Power Information.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Hardware Security (Dagstuhl Seminar 16202).
Dagstuhl Reports, 2016

2015
Randomized Multitopology Logic Against Differential Power Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Relations Between the Entropy of a Source and the Error Masking Probability for Security-Oriented Codes.
IEEE Trans. Commun., 2015

Efficient Implementation of Punctured Parallel Finite Field Multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Data-Dependent Delays as a Barrier Against Power Attacks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A New Approach to UEP-HARQ via Convolutional Codes.
IEEE Commun. Lett., 2015

Zero-latency zero-error codes for parallel asynchronous channels with arbitrary skews.
Proceedings of the 2015 IEEE Information Theory Workshop, 2015

2014
Robust Generalized Punctured Cubic Codes.
IEEE Trans. Inf. Theory, 2014

Universal Hardware for Systems With Acceptable Representations as Low Order Polynomials.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A new efficiency criterion for security oriented error correcting codes.
Proceedings of the 19th IEEE European Test Symposium, 2014

Protecting cryptographic hardware against malicious attacks by nonlinear robust codes.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
An Introduction to Robust Codes over Finite Fields.
SIAM Rev., 2013

Enhancement of Hardware Security by Hamming-Ball Based State Assignment.
Inf. Secur. J. A Glob. Perspect., 2013

On the Efficiency of Berger Codes Against Error Injection Attacks on Parallel Asynchronous Communication Channels.
Inf. Secur. J. A Glob. Perspect., 2013

2012
Punctured Karpovsky-Taubin binary robust error detecting codes for cryptographic devices.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Functional level embedded self testing for Walsh transform based adaptive hardware.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Amalgamated q-ary codes for multi-level flash memories.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
A Comment on the Karpovsky-Taubin Code.
IEEE Trans. Inf. Theory, 2011

Determining the Number of Paths in Decision Diagrams by Using Autocorrelation Coefficients.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Detection of Trojan HW by using hidden information on the system.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Generalized If-Then-Else Operator for Compact Polynomial Representation of Multi Output Functions.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
One-to-Many: Context-Oriented Code for Concurrent Error Detection.
J. Electron. Test., 2010

Fault tolerance of decomposed PLAs.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Duplication Based One-to-Many Coding for Trojan HW Detection.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
Designing fault tolerant FSM by nano-PLA.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
Reduction of Average Path Length in Binary Decision Diagrams by Spectral Methods.
IEEE Trans. Computers, 2008

Arbitrary Error Detection in Combinational Circuits by Using Partitioning.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Use of Gray Decoding for Implementation of Symmetric Functions.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

2006
Cascade Scheme for Concurrent Errors Detection.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

1999
More on the Distance Distribution of BCH Codes.
IEEE Trans. Inf. Theory, 1999

1998
Codes Correcting Phased Burst Erasures.
IEEE Trans. Inf. Theory, 1998

1997
A class of array codes correcting multiple column erasures.
IEEE Trans. Inf. Theory, 1997


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