Oskar Andersson

According to our database, Oskar Andersson authored at least 22 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments.

Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø

IEEE Trans. Very Large Scale Integr. Syst., January, 2024

2023

A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks.

Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2020

A Neural Network Engine for Resource Constrained Embedded Systems.

Zuzana Jelcicová, Adrian Mardari, Oskar Andersson, Evangelia Kasapaki, Jens Sparsø

Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

2018

A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI.

Babak Mohammadi, Oskar Andersson, Joseph Nguyen, Lorenzo Ciampolini, Andreia Cathelin, Joachim Neves Rodrigues

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography.

Shahzad Asif, Oskar Andersson, Joachim Neves Rodrigues, Yinan Kong

IET Comput. Digit. Tech., 2018

2017

Adaptive and multi-mode baseband systems for next generation wireless communication.

Farhana Sheikh, Ankit Sharma, Oskar Andersson, Mehnaz Rahman, Dongmin Yoon, Alexios Balatsoukas-Stimming, Deepak Dasalukunte, Anthony Chun

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS.

Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS.

Nafiseh Seyed Mazloum, Joachim Neves Rodrigues, Oskar Andersson, Anders Nejdel, Ove Edfors

CoRR, 2016

Logic filter cache for wide-VDD-range processors.

Alen Bardizbanyan, Oskar Andersson, Joachim Neves Rodrigues, Per Larsson-Edefors

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI.

Babak Mohammadi, Oskar Andersson, Joseph Nguyen, Lorenzo Ciampolini, Andreia Cathelin, Joachim Neves Rodrigues

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI.

Babak Mohammadi, Oskar Andersson, Xiao Luo, Masoud Nouripayam, Joachim Neves Rodrigues

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A 290 mV Sub-V_𝕋 ASIC for Real-Time Atrial Fibrillation Detection.

Oskar Andersson, Ki H. Chon, Leif Sörnmo, Joachim Neves Rodrigues

IEEE Trans. Biomed. Circuits Syst., 2015

Reconfıgurable and selectively-adaptive signal processing for multi-mode wireless communication.

Farhana Sheikh, Oskar Andersson, Ching-En Lee, Feng Xue, Chia-Hsiang Chen, Anuja Vaidya, Ankit Sharma, Tom Tetzlaff

Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS.

Oskar Andersson, Joachim Neves Rodrigues

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS.

Oskar Andersson, Babak Mohammadi, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues

Proceedings of the ESSCIRC 2014, 2014

2013

A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs.

Christoph Thomas Muller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparsø, Joachim Neves Rodrigues

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS.

Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues

Proceedings of the ESSCIRC 2013, 2013

2012

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.

Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg

Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing.

Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.

Pascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS.

Oskar Andersson, S. M. Yasser Sherazi, Joachim Neves Rodrigues

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Synthesis strategies for sub-VT systems.

Pascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011