Oscar Ruano
Orcid: 0000-0001-8275-1745
According to our database1,
Oscar Ruano
authored at least 14 papers
between 2007 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension.
IEEE Trans. Aerosp. Electron. Syst., October, 2023
RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography.
IEEE Trans. Computers, March, 2023
2022
Design and implementation of efficient QCA full-adders using fault-tolerant majority gates.
J. Supercomput., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors.
Comput. Electr. Eng., 2022
2021
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial.
Sensors, 2021
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
2011
Microelectron. Reliab., 2011
Validation and optimization of TMR protections for circuits in radiation environments.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2009
Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study.
Integr., 2009
2008
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study.
J. Signal Process. Syst., 2008
2007
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007