Oscar Guerra

Orcid: 0000-0002-1056-7209

Affiliations:
  • University of Seville, IMSE-CNM, Spain


According to our database1, Oscar Guerra authored at least 15 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
An LC-tank based DCO for low-power high-speed applications using full-custom nMOS-type varactors.
Microelectron. J., 2024

2023
ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
A Novel Design Methodology for Low-Power, Low-Noise LC-Based Digital-Controlled Oscillators.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2012
CMOS SPADs selection, modeling and characterization towards image sensors implementation.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2008
An Integrated Layout-Synthesis Approach for Analog ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007
Network AD HOC Routing Algorithm: An Application with Bluetooth.
Proceedings of the 17th International Conference on Electronics, 2007

2005
A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs.
IEEE J. Solid State Circuits, 2005

2004
A 0.35µm CMOS 17-bit@40kS/s sensor A/D interface based on a programmable-gain cascade 2-1 Sigma Delta modulator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An alternative DFT methodology to test high-resolution Sigma Delta modulators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A modem in CMOS technology for data communication on the low-voltage power line.
Integr., 2003

On the development of a MODEM for data transmission and control of electrical household appliances using the low-voltage power-line.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2000
An error-controlled methodology for approximate hierarchical symbolic analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits.
Proceedings of the 2000 Design, 2000

1999
An Accurate Error Control Mechanism for Simplification Before Generation Algorihms.
Proceedings of the 1999 Design, 1999

1998
A simplification before and during generation methodology for symbolic large-circuit analysis.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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