Oscar G. Plata

ACM Trans. Archit. Code Optim., 2014

Multicore cache hierarchies: design and programmability issues.

[BibT_eX]

[DOI]

Ramon Doallo

Concurr. Comput. Pract. Exp., 2014

Improving Signature Behavior by Irrevocability in Transactional Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Scalability Analysis of Signatures in Transactional Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013

Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2013

LS-Sig: Locality-Sensitive Signatures for Transactional Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Dealing with Reduction Operations Using Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

Parallelizing the Sparse Matrix Transposition: Reducing the Programmer Effort Using Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computational Science, 2013

Exploring Irregular Reduction Support in Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

2012

VLBI-resolution radio-map algorithms: Performance analysis of different levels of data-sharing on multi-socket, multi-core architectures.

[BibT_eX]

[DOI]

Comput. Phys. Commun., 2012

2011

Multiset signatures for transactional memory.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Spectral evolution simulation on leading multi-socket, multicore platforms.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on High Performance Computing, 2011

Unified Locality-Sensitive Signatures for Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010

Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Data Engineering and Automated Learning, 2010

2009

Experiences with Mapping Non-linear Memory Access Patterns into GPUs.

[BibT_eX]

[DOI]

Proceedings of the Computational Science, 2009

Introduction.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2009 Parallel Processing, 2009

Improving Signatures by Locality Exploitation for Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the PACT 2009, 2009

2008

Teaching the Cache Memory System Using a Reconfigurable Approach.

[BibT_eX]

[DOI]

José Ignacio Benavides

IEEE Trans. Educ., 2008

An analytical model of locality-based parallel irregular reductions.

[BibT_eX]

[DOI]

Parallel Comput., 2008

Using Padding to Optimize Locality in Scientific Applications.

[BibT_eX]

[DOI]

Proceedings of the Computational Science, 2008

2007

Maximum and Sorted Cache Occupation Using Array Padding.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

A New Parallel Sorting Algorithm based on Odd-Even Mergesort.

[BibT_eX]

[DOI]

Guillermo Ruíz

José Ignacio Benavides

Proceedings of the 15th Euromicro International Conference on Parallel, 2007

Simulating a Reconfigurable Cache System for Teaching Purposes.

[BibT_eX]

[DOI]

José Ignacio Benavides

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2006

Topic 4: Compilers for High Performance.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

2005

On the parallelization of irregular and dynamic programs.

[BibT_eX]

[DOI]

Parallel Comput., 2005

Parallel techniques in irregular codes: cloth simulation as case of study.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2005

Distributed Architecture System for Computer Performance Testing.

[BibT_eX]

[DOI]

Proceedings of the Parallel Processing and Applied Mathematics, 2005

Reducing Cache Misses by Loop Reordering.

[BibT_eX]

Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

2004

Parallelization issues of a code for physically-based simulation of fabrics.

[BibT_eX]

[DOI]

Comput. Phys. Commun., 2004

Data partitioning-based parallel irregular reductions.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2004

Optimization Techniques for Irregular and Pointer-Based Programs.

[BibT_eX]

[DOI]

Rafael Asenjo

Francisco Corbera

M. Angeles Gonzales Navarro

Proceedings of the 12th Euromicro Workshop on Parallel, 2004

A New Dependence Test Based on Shape Analysis for Pointer-Based Codes.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for High Performance Computing, 2004

Applying Loop Tiling and Unrolling to a Sparse Kernel Code.

[BibT_eX]

[DOI]

Gerardo Bandera

Proceedings of the Computational Science, 2004

Topic 11: Numerical Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003

Optimization techniques for parallel irregular reductions.

[BibT_eX]

[DOI]

J. Syst. Archit., 2003

2002

On Improving the Performance of Data Partitioning Oriented Parallel Irregular Reductions.

[BibT_eX]

[DOI]

Proceedings of the 10th Euromicro Workshop on Parallel, 2002

2001

A Data-Parallel Formulation for Divide and Conquer Algorithms.

[BibT_eX]

[DOI]

Comput. J., 2001

Improving parallel irregular reductions using partial array expansion.

[BibT_eX]

[DOI]

Proceedings of the 2001 ACM/IEEE conference on Supercomputing, 2001

Balanced, Locality-Based Parallel Irregular Reductions.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 2001

2000

Automatic parallelization of irregular applications.

[BibT_eX]

[DOI]

Parallel Comput., 2000

A Data Parallel Formulation of the Barnes-Hut Method for N -Body Simulations.

[BibT_eX]

[DOI]

Proceedings of the Applied Parallel Computing, 2000

A compiler method for the parallel execution of irregular reductions in scalable shared memory multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 14th international conference on Supercomputing, 2000

1999

An Efficient Architecture for the In-Place Fast Cosine Transform.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1999

Data-parallel support for numerical irregular problems.

[BibT_eX]

[DOI]

Parallel Comput., 1999

On Automatic Parallelization of Irregular Reductions on Scalable Shared Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998

HPF-2 Support for Dynamic Sparse Computations.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 1998

1997

Unified Framework for the Parallelization of Divide and Conquer Based Tridiagonal Systems.

[BibT_eX]

[DOI]

Parallel Comput., 1997

Modelling Superlinear Speedup on Distributed Memory Multiprocessors.

[BibT_eX]

Proceedings of the Parallel Computing: Fundamentals, 1997

An efficient architecture for the in place fast cosine transform.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1995

Image Template Matching on Distributed Memory and Vector Multiprocessors.

[BibT_eX]

Proceedings of the Parallel Computing: State-of-the-Art and Perspectives, 1995

1994

Combining static and dynamic scheduling on distributed-memory multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 8th international conference on Supercomputing, 1994

Adapting PICL and ParaGraph Tools to Transputer-Based Multicomputers.

[BibT_eX]

[DOI]

Vicente Blanco Pérez

Proceedings of the High-Performance Computing and Networking, 1994

Vectorization of the Radix r Self-Sorting FFT.

[BibT_eX]

[DOI]

Proceedings of the Parallel Processing: CONPAR 94, 1994

1993

An Efficient Processor Allocation for Nested Parallel Loops on Distributed Memory Hypercubes.

[BibT_eX]

[DOI]

Parallel Process. Lett., 1993

1992

Design of parallel algorithms for a distributed memory hypercube.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1992

1991

Modified Gram-Schmidt QR Factorization on Hypercube SIMD Computers.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1991

1990

Image template matching on hypercube SIMD computers.

[BibT_eX]

[DOI]

José Ignacio Benavides Benítez

José María Carazo

Signal Process., 1990

A reliability model for multiprocessor networks with degradable nodes.

[BibT_eX]

[DOI]

Javier D. Bruguera