Osamu Nomura

According to our database, Osamu Nomura authored at least 14 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers.

Soshi Hirayae, Kanta Yoshioka, Atsuki Yokota, Ichiro Kawashima, Yuichiro Tanaka, Yuichi Katori, Osamu Nomura, Takashi Morie, Hakaru Tamukoh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

CMOS digital-analog mixed signal VLSI implementation of a hippocampus-inspired model.

Yuka Shishido, Osamu Nomura, Katsumi Tateno, Hakaru Tamukoh, Takashi Morie

Proceedings of the International Joint Conference on Neural Networks, 2024

A Hippocampus-Inspired Environment-Specific Knowledge Acquisition System Utilizing Common Knowledge with Contextual Information.

Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Osamu Nomura, Katsumi Tateno, Takashi Morie

Proceedings of the International Joint Conference on Neural Networks, 2024

Robust Binary Encoding for Ternary Neural Networks Toward Deployment on Emerging Memory.

Ninnart Fuengfusin, Hakaru Tamukoh, Osamu Nomura, Takashi Morie

Proceedings of the International Joint Conference on Neural Networks, 2024

2023

FPGA Implementation of a Chaotic Boltzmann Machine Annealer.

Kanta Yoshioka, Yuichi Katori, Yuichiro Tanaka, Osamu Nomura, Takashi Morie, Hakaru Tamukoh

Proceedings of the International Joint Conference on Neural Networks, 2023

Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-Volatile Memory with Write-Errors.

Ninnart Fuengfusin, Hakaru Tamukoh, Yuichiro Tanaka, Osamu Nomura, Takashi Morie

Proceedings of the International Joint Conference on Neural Networks, 2023

2022

Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT.

Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh

IEEE Trans. Ind. Informatics, 2022

Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks.

Osamu Nomura, Yusuke Sakemi, Takeo Hosomi, Takashi Morie

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2007

Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach.

Osamu Nomura, Takashi Morie

Proceedings of the Neural Information Processing, 14th International Conference, 2007

2006

An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture.

Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata

IEICE Trans. Electron., 2006

2005

A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations.

Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata

Proceedings of the Advances in Natural Computation, First International Conference, 2005

2004

A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture.

Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata

J. Intell. Fuzzy Syst., 2004

A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition.

Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata

Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2004

2003

A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture.

Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata

Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2003