Osamu Nishii
According to our database1,
Osamu Nishii
authored at least 14 papers
between 1994 and 2011.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2011
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.
IEICE Trans. Electron., 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU.
Microprocess. Microsystems, 2009
2008
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Syst. Comput. Jpn., 2006
IEICE Trans. Electron., 2006
2005
SIGARCH Comput. Archit. News, 2005
A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.
IEICE Trans. Electron., 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
1998
1994
Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994