Osama Daifallah Al-Khaleel

Orcid: 0000-0003-0585-2619

According to our database1, Osama Daifallah Al-Khaleel authored at least 20 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Mental Health Monitoring and Detection Based on Machine Learning and IoT Data.
Int. J. Inf. Technol. Decis. Mak., July, 2024

2023
Building a neural speech recognizer for quranic recitations.
Int. J. Speech Technol., December, 2023

An ECC processor for IoT using Edwards curves and DFT modular multiplication.
Clust. Comput., April, 2023

Design of High Speed BCD Adder Using CMOS Technology.
IEEE Access, 2023

2022
FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells.
J. Univers. Comput. Sci., 2022

Ransomware-Resilient Self-Healing XML Documents.
Future Internet, 2022

2021
FPGA Implementation of Data Flow Graphs for Digital Signal Processing Applications.
Int. J. Commun. Networks Inf. Secur., 2021

2015
Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication.
J. Circuits Syst. Comput., 2015

2014
Utilizing Mobile Devices' Tactile Feedback for Presenting Braille Characters: An Optimized Approach for Fast Reading and Long Battery Life.
Interact. Comput., 2014

OpenSPARC Processor Evaluation Using Virtex-5 FPGA and High Performance Embedded Computing (HPEC) Benchmark Suite.
Int. J. Embed. Real Time Commun. Syst., 2014

DDoS protection as a service: hiding behind the giants.
Int. J. Comput. Sci. Eng., 2014

2013
High performance FPGA-based decimal-to-binary conversion schemes for decimal arithmetic.
Microprocess. Microsystems, 2013

2012
An Innovative Information Hiding Technique Utilizing Cumulative Peak Histogram Regions.
J. Syst. Inf. Technol., 2012

2011
Fast binary/decimal adder/subtractor with a novel correction-free BCD addition.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Fast and compact binary-to-BCD conversion circuits for decimal multiplication.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
An efficient compression technique using Lempel-Ziv algorithm based on dynamic source encoding scheme.
Int. J. Inf. Commun. Technol., 2010

2009
Arabic Text Compression Technique Based on Lempel-Ziv Algorithm.
Proceedings of the 2009 International Conference on Information & Knowledge Engineering, 2009

2007
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Large Scale Adaptable Multiplier for Cryptographic Applications.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006


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