Orlando Moreira

Orcid: 0000-0003-2362-4169

According to our database1, Orlando Moreira authored at least 42 papers between 2000 and 2024.

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Bibliography

2024
CATS: Combined Activation and Temporal Suppression for Efficient Network Inference.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024

ELSE: Efficient Deep Neural Network Inference Through Line-Based Sparsity Exploration.
Proceedings of the Computer Vision - ECCV 2024, 2024

2023
Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators.
IEEE Trans. Parallel Distributed Syst., April, 2023


STAR: Sparse Thresholded Activation under partial-Regularization for Activation Sparsity Exploration.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2022
ARTS: An adaptive regularization training schedule for activation sparsity exploration.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2020
Evolutionary multi-level acyclic graph partitioning.
J. Heuristics, 2020

NeuronFlow: a neuromorphic processor architecture for Live AI applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

NeuronFlow: A Hybrid Neuromorphic - Dataflow Processor Architecture for AI Workloads.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

SpArNet: Sparse Asynchronous Neural Network execution for energy efficient inference.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

2017
Special Section: Integrating Dataflow, Embedded Computing and Architecture.
ACM Trans. Design Autom. Electr. Syst., 2017

Evolutionary Acyclic Graph Partitioning.
CoRR, 2017

Graph Partitioning with Acyclicity Constraints.
Proceedings of the 16th International Symposium on Experimental Algorithms, 2017

Automatic Control Flow Generation for OpenVX Graphs.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Modeling & analysis of an LTE-Advanced receiver using mode-controlled dataflow.
Microprocess. Microsystems, 2016

Buffer allocation for real-time streaming applications running on heterogeneous multi-processors without back-pressure.
J. Syst. Archit., 2016

Response modeling runtime schedulers for timing analysis of self-timed dataflow graphs.
J. Syst. Archit., 2016

Automatic HAL generation for embedded multiprocessor systems.
Proceedings of the 2016 International Conference on Embedded Software, 2016

2015
Mode-controlled data-flow modeling of real-time memory controllers.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Buffer Allocation for Dynamic Real-Time Streaming Applications Running on a Multi-processor without Back-Pressure.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

FP-scheduling for mode-controlled dataflow: a case study.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Buffer allocation for real-time streaming on a multi-processor without back-pressure.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Analyzing preemptive fixed priority scheduling of data flow graphs.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Mode-Controlled Dataflow based modeling & analysis of a 4G-LTE receiver.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Cyclo-Static Data Flow Model for TDM.
Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014

2013
Throughput-constrained voltage and frequency scaling for real-time heterogeneous multiprocessors.
Proceedings of the 28th Annual ACM Symposium on Applied Computing, 2013

2012
Hard-Real-Time Scheduling on a Weakly Programmable Multi-core Processor with Application to Multi-standard Channel Decoding.
Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012

A new data flow analysis model for TDM.
Proceedings of the 12th International Conference on Embedded Software, 2012

Worst-case throughput analysis of real-time dynamic streaming applications.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Analyzing synchronous dataflow scenarios for dynamic software-defined radio applications.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Power Minimisation for Real-Time Dataflow Applications.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Designing next-generation real-time streaming systems.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Buffer Sizing for Rate-Optimal Single-Rate Data-Flow Scheduling Revisited.
IEEE Trans. Computers, 2010

Disciplined Multi-core Programming in C.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2010

2007
Self-Timed Scheduling Analysis for Real-Time Applications.
EURASIP J. Adv. Signal Process., 2007

Online resource management in a multiprocessor with a network-on-chip.
Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

2005
Multiprocessor Resource Allocation for Hard-Real-Time Streaming with a Dynamic Job-Mix.
Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 2005

2004
Predictable Embedded Multiprocessor System Design.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

2000
Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis.
Proceedings of the Field-Programmable Logic and Applications, 2000

A Novel Approach to Minimizing the Logic of Combinatorial Multiplexing Circuits in Product-Term-Based Hardware.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000


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