Oriol Roig

According to our database1, Oriol Roig authored at least 11 papers between 1994 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2002
Checking Delay-Insensitivity: 10<sup>4</sup> Gates and Beyond.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
Symbolic Analysis of Bounded Petri Nets.
IEEE Trans. Computers, 2001

1998
Structural methods for the synthesis of speed-independent circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Review of General and Toeplitz Vector Bidiagonal Solvers.
Parallel Comput., 1996

1995
A new look at the conditions for the synthesis of speed-independent circuits.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Checking signal transition graph implementability by symbolic BDD traversal.
Proceedings of the 1995 European Design and Test Conference, 1995

Hierarchical gate-level verification of speed-independent circuits.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets.
Proceedings of the Application and Theory of Petri Nets 1995, 1995

1994
A generalized vision of some parallel bidiagonal systems solvers.
Proceedings of the 8th international conference on Supercomputing, 1994

Petri Net Analysis Using Boolean Manipulation.
Proceedings of the Application and Theory of Petri Nets 1994, 1994


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