Onur Tunali

Orcid: 0000-0002-2326-0708

According to our database1, Onur Tunali authored at least 8 papers between 2015 and 2019.

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Bibliography

2019
A Fast Logic Mapping Algorithm for Multiple-Type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays.
IEEE Trans. Emerg. Top. Comput., 2019

2018
Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation.
IEEE Micro, 2018

A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays.
ACM Comput. Surv., 2018

Integrated Synthesis Methodology for Crossbar Arrays.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Logic synthesis and defect tolerance for memristive crossbar arrays.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Yield analysis of nano-crossbar arrays for uniform and clustered defect distributions.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2015
Defect tolerance in diode, FET, and four-terminal switch based nano-crossbar arrays.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015


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