Ondrej Novák

According to our database, Ondrej Novák authored at least 50 papers between 1988 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Nonlinear compression block codes: Exact and random search strategy.

Ondrej Novák

Microprocess. Microsystems, 2023

Deterministic Search Strategy of Compression Codes.

Ondrej Novák

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022

Nonlinear Compression Block Codes Search Strategy.

Ondrej Novák

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

Search Strategy of Large Nonlinear Block Codes.

Ondrej Novák

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020

Decompressors using nonlinear codes.

Ondrej Novák, Martin Rozkovec, Jan Plíva

Microprocess. Microsystems, 2020

2019

International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková

Proceedings of the IEEE International Test Conference, 2019

Combinational Decompressors with Nonlinear Codes.

Ondrej Novák, Martin Rozkovec, Jan Plíva

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Nonlinear Compression Codes Used In IC Testing.

Ondrej Novák

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Portable Bluetooth Microsystem for Electrochemically Modulated Nitric Oxide-Releasing Catheters.

Ondrej Novák, Kamila K. Konopinska, Mark E. Meyerhoff, Richard B. Brown

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018

Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017).

Zoran Stamenkovic, Ondrej Novák, Witold A. Pleskacz

Microelectron. Reliab., 2018

Test response compaction method with improved detection and diagnostic abilities.

Ondrej Novák, Zdenek Plíva

Microelectron. Reliab., 2018

Test Compression Using Extended Nonlinear Binary Codes.

Ondrej Novák

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017

Sequential Test Decompressors with Fast Tester Bits Wide-Spreading.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

J. Circuits Syst. Comput., 2017

Extended binary nonlinear codes and their application in testing and compression.

Ondrej Novák

Proceedings of the 22nd IEEE European Test Symposium, 2017

Logic testing with test-per-clock pattern loading and improved diagnostic abilities.

Ondrej Novák, Zdenek Plíva

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016

An empirical model of UWB large-scale signal fading in neocortical research.

Ondrej Novák, Richard B. Brown

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Test Decompressor Effectivity Improvement.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Sequential test decompressors with fast variable wide spreading.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

Formation and disruption of tonotopy in a large-scale model of the auditory cortex.

Markéta Tomková, Jakub Tomek, Ondrej Novák, Ondrej Zelenka, Josef Syka, Cyril Brom

J. Comput. Neurosci., 2015

Test compression for circuits with multiple scan chains.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 16th Latin-American Test Symposium, 2015

LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

A highly flexible reconfigurable system on a Xilinx FPGA.

Tomas Drahonovsky, Martin Rozkovec, Ondrej Novák

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Test-data compression with low number of channels and short test time.

Ondrej Novák, Jiri Jenícek, Martin Rozkovec

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

Relocation of reconfigurable modules on Xilinx FPGA.

Tomas Drahonovsky, Martin Rozkovec, Ondrej Novák

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Test pattern decompression in parallel scan chain architecture.

Martin Chloupek, Jiri Jenícek, Ondrej Novák, Martin Rozkovec

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

An evaluation of the application dependent FPGA test method.

Martin Rozkovec, Jiri Jenícek, Ondrej Novák

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

On test time reduction using pattern overlapping, broadcasting and on-chip decompression.

Martin Chloupek, Ondrej Novák, Jiri Jenícek

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

Scan chain configuration method for broadcast decompressor architecture.

Martin Chloupek, Ondrej Novák

Proceedings of the 12th Latin American Test Workshop, 2011

Advanced scan chain configuration method for broadcast decompressor architecture.

Jiri Jenícek, Ondrej Novák, Martin Chloupek

Proceedings of the 9th East-West Design & Test Symposium, 2011

Test vector overlapping based compression tool for narrow test access mechanism.

Jiri Jenícek, Martin Rozkovec, Ondrej Novák

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

Application dependent FPGA testing method using compressed deterministic test vectors.

Martin Rozkovec, Jiri Jenícek, Ondrej Novák

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

COMPAS - Advanced test compressor.

Jiri Jenícek, Ondrej Novák

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Application Dependent FPGA Testing Method.

Martin Rozkovec, Jiri Jenícek, Ondrej Novák

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Reconfigurable Fault-Tolerant System Sychronization.

Jan Balach, Ondrej Novák

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Structural test of programmed FPGA circuits.

Martin Rozkovec, Ondrej Novák

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2007

A Novel Emulation Technique that Preserves Circuit Structure and Timing.

Leos Kafka, Martin Danek, Ondrej Novák

Proceedings of the International Symposium on System-on-Chip, 2007

Test Pattern Compression Based on Pattern Overlapping.

Jiri Jenícek, Ondrej Novák

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Conference Reports.

Subhasish Mitra, Ondrej Novák, Hana Kubátová, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar

IEEE Des. Test Comput., 2006

Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW.

Martin Stáva, Ondrej Novák

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.

Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration.

Martin Stáva, Ondrej Novák

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

FPGA-based Fault Simulator.

Leos Kafka, Ondrej Novák

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005

COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits.

Ondrej Novák, Jirí Zahrádka, Zdenek Plíva

Proceedings of the Dependable Computing, 2005

2004

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.

Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa

J. Electron. Test., 2004

2003

Comparison of Test Pattern Decompression Techniques.

Ondrej Novák

Proceedings of the 2003 Design, 2003

2001

Test-per-Clock Testing of the Circuits with Scan.

Ondrej Novák, Jiri Nosek

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Test Pattern Decompression Using a Scan Chain.

Ondrej Novák, Jiri Nosek

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000

On Using Deterministic Test Sets in BIST.

Ondrej Novák, Jiri Nosek

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

1999

Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata.

Ondrej Novák

Proceedings of the Dependable Computing, 1999

1988

Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage.

P. Golan, Ondrej Novák, Jan Hlavicka

IEEE Trans. Computers, 1988