Omid Shoaei
Orcid: 0000-0002-8280-1834Affiliations:
- University of Tehran
According to our database1,
Omid Shoaei
authored at least 117 papers
between 1994 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
-
on ece.ut.ac.ir
On csauthors.net:
Bibliography
2024
A Reconfigurable, Nonlinear, Low-Power, VCO-Based ADC for Neural Recording Applications.
Sensors, October, 2024
A 69MHz-Bandwidth 40V/μ s-Slew-Rate 3n V/√Hz-Noise 4.5 μ V-Offset Chopper Operational Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024
A compact bipolar high-voltage pulser with a novel transistor gate-source protection scheme for ultrasound imaging applications.
Int. J. Circuit Theory Appl., May, 2024
2023
IEEE Trans. Biomed. Circuits Syst., October, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
A 69MHz-Bandwidth 40V/μs-Slew-rate 3nV/√Hz-Noises 4.5μV-Offset Chopper Operational Amplifier.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
Fast Background Calibration of Linear and Non-Linear Errors in Pipeline Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Class-E Power and Data Transmitter With Improved Data Rate to Carrier Frequency Ratio for Medical Implants.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
A 7.2µW Magnitude/Phase Bio-impedance Measurement Front-End with PWM Output in 0.18µm CMOS.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Int. J. Circuit Theory Appl., 2020
2019
A comprehensive circuit model for evaluating the response of silicon photomultipliers in continuous wave light regime.
Int. J. Circuit Theory Appl., 2019
Proceedings of the Signal Processing: Algorithms, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Enhanced Power-Delivered-to-Load Through Planar Multiple-Harmonic Wireless Power Transmission.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 1.55 μW Bio-Impedance Measurement System for Implantable Cardiac Pacemakers in 0.18 μm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2018
Mixed-Signal IC With Pulse Width Modulation Wireless Telemetry for Implantable Cardiac Pacemakers in 0.18-μm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2018
Microelectron. J., 2018
Microelectron. J., 2018
Int. J. Circuit Theory Appl., 2018
A Fully Fail-Safe Capacitive-Based Charge Metering Method for Active Charge Balancing in Deep Brain Stimulation.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Two-electrode impedance-sensing cardiac rhythm monitor for charge-aware shock delivery in cardiac arrest.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An aging-aware model for the leakage power of nanoscaled digital integrated circuits in IoT era.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Extended coupling-range wireless power transfer using 0× / 4× resonant regulating rectifier.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
A Power optimized switched-capacitor based approach in voltage-controlled cardiac stimulation.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
A double-carrier wireless power and data telemetry for implantable biomedical systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2014
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2011
Microelectron. J., 2011
IET Circuits Devices Syst., 2011
2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Electron. Express, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
New technique in design of active rf cmos mixers for low flicker noise and high conversion gain.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEICE Trans. Electron., 2007
A new reconfigurable LNA enhanced by programmable load and capacitive feedback for multi-standard applications.
IEICE Electron. Express, 2007
IEICE Electron. Express, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Analysis of the Clock Jitter Effects in a Time Invariant Model of Continuous Time Delta Sigma Modulators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A New Infrastructure for Digital Pre-Filtering in Multi-bit Continuous Time Delta Sigma Modulators.
IEICE Trans. Electron., 2006
A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications.
IEICE Trans. Electron., 2006
IEICE Electron. Express, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A low power, transverse analog FIR filter for feed forward equalization of gigabit Ethernet.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A novel structure for the design of 2-1-1 cascaded continuous time delta sigma modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Double-sampling single-loop sigma-delta modulator topologies for broadband applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
A New Approach for DAC Non-linearity Compensation in Continuous Time Delta Sigma Modulators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE Trans. Instrum. Meas., 2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
A New Method for Elimination of the Clock Jitter Effects in Continuous Time Delta-Sigma Modulators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
A Simplified Illustration of Arbitrary DAC Waveform Effects in Continuous Time Delta-Sigma Modulators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
A 2/5mW CMOS Delta Sigma modulator employed in an improved GSM/UMTS receiver structure.
IEICE Electron. Express, 2005
IEICE Electron. Express, 2005
IEICE Electron. Express, 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A low-power ΣΔ modulator with low capacitor spread for multi-standard receiver applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A dynamic start-up circuit for low voltage CMOS current mirrors with power-down support.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A novel fully-differential class AB folded-cascode OTA for switched-capacitor applications.
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Power spectral density estimation of the clock jitter in a continuous time Delta Sigma modulator with non return to-zero DAC waveform.
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Microelectron. J., 2004
IEICE Electron. Express, 2004
Return to-zero feedback insertion in a continuous time Delta-Sigma modulator for excess loop delay compensation.
IEICE Electron. Express, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A 10-bit, 3.3-V, 60MSample/s, combined radix<2 and 1.5-bit/stage pipelined analog-to-digital converter.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An analytical model for the slewing behavior of CMOS two-stage operational transconductance amplifiers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-µm CMOS [convereter read converter].
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 Design, 2004
2003
On the parasitic-sensitivity of switched-capacitor summing-integrator structures for ΣΔ modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications.
Integr., 2003
Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A low-power design methodology for high-resolution pipelined analog-to-digital converters.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25µm CMOS.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A new compensation technique for two-stage CMOS operational transconductance amplifiers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
An analytical approach to the estimation of the spurious-free dynamic range in pipeline A/D converters.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A 1.5-V 12-bit 75M-samples/s fully-differential low-power sample-and-hold amplifier in 0.25-μm CMOS.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
An analytical approach to the estimation of dynamic non-linearity parameters in pipeline A/D converters.
Proceedings of the ESSCIRC 2003, 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-um CMOS.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
A 1.4 GHz/2.7 V programmable frequency divider for DRRS standard in 0.6 μm CMOS process.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Kalman-filtering timing recovery scheme for orthogonal frequency domain multiplexing (OFDM) systems.
Proceedings of the IEEE International Conference on Acoustics, 2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994