Omid Hashemipour

J. Circuits Syst. Comput., 2022

2021

Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters.

[BibT_eX]

[DOI]

Bardia Babaei

Int. J. Circuit Theory Appl., 2021

Mismatch error shaping of DAC unit elements in multibit ∆Σ modulators using a novel unified ADC/DAC.

[BibT_eX]

[DOI]

Leila Sharifi

Turkish J. Electr. Eng. Comput. Sci., 2021

2019

An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

A charge sharing-based switching scheme for SAR ADCs.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2019

Energy-Efficient and Area-Efficient Switching Schemes for SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018

Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion.

[BibT_eX]

[DOI]

Farshad Moradi

IEEE Trans. Very Large Scale Integr. Syst., 2018

An energy-efficient DAC switching algorithm based on charge recycling method for SAR ADCs.

[BibT_eX]

[DOI]

Microelectron. J., 2018

Two-Dimensional Structure Compatible with DEM Methods Utilizing in DACs.

[BibT_eX]

[DOI]

Mehdi Bandali

J. Circuits Syst. Comput., 2018

A Class-AB Bulk-Driven Amplifier with Enhanced Transconductance Using Quasi-Floating Gate Method.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2018

A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates.

[BibT_eX]

[DOI]

Mohammad Mehdi Panahi

Integr., 2018

A High Slew Rate CMOS OTA with Dynamic Current Boosting Paths.

[BibT_eX]

[DOI]

Farshad Moradi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Low Power Current Conveyor Based Continuous Time Sigma Delta Modulator.

[BibT_eX]

[DOI]

Reza Chavoshisani

J. Low Power Electron., 2017

A 63-dB gain OTA operating in subthreshold with 20-nW power consumption.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2017

Design and Analysis of an Ultra-Low-Power Second-Order Asynchronous Delta-Sigma Modulator.

[BibT_eX]

[DOI]

Farshad Moradi

Circuits Syst. Signal Process., 2017

2016

Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

2015

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2015

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2015

New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources.

[BibT_eX]

[DOI]

Int. J. High Perform. Syst. Archit., 2015

2014

A Flexible Design for Optimization of Hardware Architecture in Distributed Arithmetic based FIR Filters.

[BibT_eX]

[DOI]

Fazel Sharifi

Saba Amanollahi

Mohammad Amin Taherkhani

CoRR, 2014

2013

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic.

[BibT_eX]

[DOI]

Microelectron. J., 2013

Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors.

[BibT_eX]

[DOI]

Int. J. High Perform. Syst. Archit., 2013

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2013

Dramatically Low-Transistor-Count High-Speed Ternary Adders.

[BibT_eX]

[DOI]

Reza Faghih Mirzaee

Mojtaba Maleknejad

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

2012

A low-variation on-resistance CMOS sampling switch for high-speed high-performance applications.

[BibT_eX]

[DOI]

Mohammad Reza Asgari

IEICE Electron. Express, 2012

Design and Evaluation of CNFET-Based Quaternary Circuits.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2012

High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2012

2011

A high-speed current conveyor based current comparator.

[BibT_eX]

[DOI]

Reza Chavoshisani

Microelectron. J., 2011

A New Switched opamp Approach for Improving the Operation of Auto-Reset Switched-capacitor Filters.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2011

Body effect compensation of analog switches using variable voltage function.

[BibT_eX]

[DOI]

Mohammad Reza Asgari

IEICE Electron. Express, 2011

A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders.

[BibT_eX]

[DOI]

Akbar Doostaregan

Seyyed Hossein Pishgar Komleh

Fuzzy Sets Syst., 2011

A reliable full-swing low-distortion CMOS bootstrapped sampling switch.

[BibT_eX]

[DOI]

Mohammad Reza Asgari

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

A simple time domain approach to noise analysis of switched capacitor circuits.

[BibT_eX]

[DOI]

Mohammad Rashtian

Ali Mohammad Afshin Hemmatyar

IEICE Electron. Express, 2010

2009

Two new low-power Full Adders based on majority-not gates.

[BibT_eX]

[DOI]

Reza Faghih Mirzaee

Babak Mazloom Nezhad

Microelectron. J., 2009

An energy efficient full adder cell for low voltage.

[BibT_eX]

[DOI]

Mehrdad Maeen

Amir Sabbagh Molahosseini

IEICE Electron. Express, 2009

2008

An efficient architecture for designing reverse converters based on a general three-moduli set.

[BibT_eX]

[DOI]

Ali Jalali

J. Syst. Archit., 2008

A low voltage bootstrapped switch based on zero DC offset input voltage.

[BibT_eX]

[DOI]

Alihosein Sepahvand

IEICE Electron. Express, 2008

Ultra high speed Full Adders.

[BibT_eX]

[DOI]

Reza Faghih Mirzaee

Babak Mazloom Nezhad