Omid Fatemi

Orcid: 0000-0001-9654-0607

According to our database1, Omid Fatemi authored at least 55 papers between 1995 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
A General Model for Detecting Learner Engagement: Implementation and Evaluation.
CoRR, 2024

2022
A novel virtual machine placement algorithm using RF element in cloud infrastructure.
J. Supercomput., 2022

2021
Toward a general framework for jointly processor-workload empirical modeling.
J. Supercomput., 2021

A crowdsourcing approach to construct mono-lingual plagiarism detection corpus.
Int. J. Digit. Libr., 2021

2020
DCMI: A Scalable Strategy for Accelerating Iterative Stencil Loops on FPGAs.
ACM Trans. Archit. Code Optim., 2020

2019
Multi-objective algorithms for the application mapping problem in heterogeneous multiprocessor embedded system design.
J. Supercomput., 2019

On the use of word embedding for cross language plagiarism detection.
Intell. Data Anal., 2019

2018
Run-time mapping algorithm for dynamic workloads using association rule mining.
J. Syst. Archit., 2018

Moving towards grey-box predictive models at micro-architecture level by investigating inherent program characteristics.
IET Comput. Digit. Tech., 2018

Run-time Mapping Algorithm for Dynamic Workloads on Heterogeneous MPSoCs Platforms.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
Run-time mapping algorithm for dynamic workloads using process merging transformations.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

A Cloud-Based Multi-threaded Implementation of View Synthesis System.
Proceedings of the 19th IEEE International Symposium on Multimedia, 2017

DTP: Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC Applications.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Run-time resource allocation for embedded Multiprocessor System-on-Chip using tree-based design space exploration.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2016
New R-D Optimization Criterion for Fast Mode Decision Algorithms in Video Coding and Transrating.
IEEE Trans. Circuits Syst. Video Technol., 2016

Novel Heuristic Mapping Algorithms for Design Space Exploration of Multiprocessor Embedded Architectures.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Algorithms and Corpora for Persian Plagiarism Detection - Overview of PAN at FIRE 2016.
Proceedings of the Text Processing, 2016

2015
Developing Bilingual Plagiarism Detection Corpus Using Sentence Aligned Parallel Corpus: Notebook for PAN at CLEF 2015.
Proceedings of the Working Notes of CLEF 2015, 2015

2014
An R-D optimized transcoding resilient motion vector selection.
EURASIP J. Adv. Signal Process., 2014

Electronic Theses and Dissertations in CRIS.
Proceedings of the 12th International Conference on Current Research Information Systems, 2014

National Open Access Scientific Articles Registration System (NOSARS).
Proceedings of the 12th International Conference on Current Research Information Systems, 2014

2012
A Two-Piece R-D Model for Hybrid Video Coding and Its Application in Fast Mode Decision.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

CTIS, Policy Making Body for National Research Information System in IRAN.
Proceedings of the 11th International Conference on Current Research Information Systems, 2012

Tag Based Recommender System for Social Bookmarking Sites.
Proceedings of the International Conference on Advances in Social Networks Analysis and Mining, 2012

2011
Design space pruning of MPSoCs using weighted sub-sampling.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

An MOPSO method for mapping multimedia applications onto MP-SOC architectures.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
Parallel merged multiplier-accumulator coprocessor optimized for digital filters.
Comput. Electr. Eng., 2010

SEMAT, National Current Research Information System for Iran.
Proceedings of the 10th International Conference on Current Research Information Systems, 2010

2009
An improved R-D optimized motion estimation method for video coding.
Proceedings of the 2009 Picture Coding Symposium, 2009

A cost-error optimized architecture for 9/7 lifting based Discrete Wavelet Transform with balanced pipeline stages.
Proceedings of the IEEE International Conference on Acoustics, 2009

2008
Unequal Error Protection for the Scalable Extension of H.264/AVC Using Genetic Algorithm.
Proceedings of the Advances in Computer Science and Engineering, 2008

2007
Two Level Cost-Quality Optimization of 9-7 Lifting-Based Discrete Wavelet Transform.
Proceedings of the International Conference on Image Processing, 2007

Pattern-Based Error Recovery of Low Resolution Subbands in JPEG2000.
Proceedings of the International Conference on Image Processing, 2007

A Split Method for Optimized Cost-Quality Hardware Implementation of Lifting-Based Discrete Wavelet Transform.
Proceedings of the IEEE International Conference on Acoustics, 2007

Improve text classification accuracy based on classifier fusion methods.
Proceedings of the 10th International Conference on Information Fusion, 2007

2006
Ant colony based routing architecture for minimizing hot spots in NOCs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Muli-Issue Multi-Threaded Stream Processor.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

A New Multi-Layered Coding Sequence for JPEG2000 with Reduced Memory Requirement.
Proceedings of the International Conference on Image Processing, 2006

A Non-Iterative R-D Optimization Algorithm for Rate-Constraint Problems.
Proceedings of the International Conference on Image Processing, 2006

An Efficient Deblocking Filter with Self-Transposing Memory Architecture For H.264/AVC.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

A Frame Layer Bit Allocation for H.264 Based on Frame Complexity.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

A Fast Two Dimensional Deblocking Filter for H.264/AVC Video Coding.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Efficient Hardware Implementation for H.264/AVC Motion Estimation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Efficient Self-Transposing Memory Structure for 32-bit Video Processors.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Dual Mode Architecture for Deblocking Filtering in H.264/AVC Video Coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A novel efficient rate control algorithm for hardware implementation in JPEG2000.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2003
Novel efficient architecture for JPEG2000 entropy coder.
Proceedings of the Visual Communications and Image Processing 2003, 2003

A pipeline memory-efficient programmable architecture for the 2D discrete wavelet transform using lifting scheme.
Proceedings of the Visual Communications and Image Processing 2003, 2003

A modified method for codebook design with neural network in VQ sed image compression.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Multimedia extensions for DLX processor.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Very fast bit allocation algorithm, based on simplified R-D curve modeling.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

1998
Fractal engine: an affine video processor core for multimedia applications.
IEEE Trans. Circuits Syst. Video Technol., 1998

1995
Persian cursive script recognition.
Proceedings of the Third International Conference on Document Analysis and Recognition, 1995


  Loading...