Omayma Matoussi

According to our database1, Omayma Matoussi authored at least 6 papers between 2017 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation.
Integr., 2019

2018
A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Detecting Software Cache Coherence Violations in MPSoC Using Traces Captured on Virtual Platforms.
ACM Trans. Embed. Comput. Syst., 2017

Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Loop aware IR-level annotation framework for performance estimation in native simulation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017


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