Om Prakash Gangwal
According to our database1,
Om Prakash Gangwal
authored at least 12 papers
between 2001 and 2005.
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Bibliography
2005
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification.
Proceedings of the 2005 Design, 2005
2004
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004
Proceedings of the 2004 Design, 2004
2003
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
2002
IEEE Des. Test Comput., 2002
C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems.
Des. Autom. Embed. Syst., 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Proceedings of the Coordination Models and Languages, 5th International Conference, 2002
2001
A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001