Oluseyi A. Ayorinde

According to our database, Oluseyi A. Ayorinde authored at least 7 papers between 2013 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

FPNA: A Reconfigurable Accelerator for AI Inference at the Edge.

Peter Gadfort, Oluseyi A. Ayorinde

Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

2019

A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications.

Christopher J. Lukas, Farah B. Yahya, Jacob Breiholz, Abhishek Roy, Xing Chen, Harsh N. Patel, Ningxi Liu, Avish Kosari, Shuo Li, Divya Akella Kamakshi, Oluseyi A. Ayorinde, David D. Wentzloff, Benton H. Calhoun

IEEE Trans. Biomed. Circuits Syst., 2019

2018

FGC: A Tool-flow for Generating and Configuring Custom FPGAs(Abstract Only).

Oluseyi A. Ayorinde, He Qi, Benton H. Calhoun

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2016

An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating.

He Qi, Oluseyi A. Ayorinde, Benton H. Calhoun

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs.

He Qi, Oluseyi A. Ayorinde, Yu Huang, Benton H. Calhoun

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Using island-style bi-directional intra-CLB routing in low-power FPGAs.

Oluseyi A. Ayorinde, He Qi, Yu Huang, Benton H. Calhoun

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2013

Circuit optimizations to minimize energy in the global interconnect of a low-power-FPGA (abstract only).

Oluseyi A. Ayorinde, Benton H. Calhoun

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013