Olivier Temam
According to our database1,
Olivier Temam
authored at least 107 papers
between 1992 and 2020.
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Bibliography
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the Workshop on Trends in Machine-Learning (and impact on computer architecture), 2017
2016
Commun. ACM, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
ACM Trans. Comput. Syst., 2015
Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
ACM Trans. Archit. Code Optim., 2015
Int. J. Parallel Program., 2015
Neuromorphic accelerators: a comparison between neuroscience and machine-learning approaches.
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
Proceedings of the Federated Computing Research Conference, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015
2014
Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach.
ACM Trans. Archit. Code Optim., 2014
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 2014 International Conference on Compilers, 2014
The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators.
Proceedings of the 2014 International Conference on Compilers, 2014
DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014
Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
BenchNN: On the broad potential application scope of hardware neural network accelerators.
Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012
2011
Int. J. Parallel Program., 2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
2010
ACM Trans. Archit. Code Optim., 2010
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010
ArchExplorer.org: A methodology for facilitating a fair Comparison of research ideas.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
Proceedings of the 2010 International Conference on Compilers, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Proceedings of the High Performance Embedded Architectures and Compilers, 2009
2008
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs.
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Trans. High Perform. Embed. Archit. Compil., 2007
Trans. High Perform. Embed. Archit. Compil., 2007
UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development.
IEEE Comput. Archit. Lett., 2007
MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007
Fast compiler optimisation evaluation using code-feature based performance prediction.
Proceedings of the 4th Conference on Computing Frontiers, 2007
2006
Load squared: Adding logic close to memory to reduce the latency of indirect loads in embedded and general systems.
J. Embed. Comput., 2006
Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory Hierarchies.
Int. J. Parallel Program., 2006
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
Automatic performance model construction for the fast software exploration of new hardware designs.
Proceedings of the 2006 International Conference on Compilers, 2006
2005
Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios.
SIGARCH Comput. Archit. News, 2005
Symbiotic Processing: Toward a Better Balance Between Architecture, Compiler and User Efforts.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Characterizing Self-developing Biological Neural Networks: A First Step Towards Their Application to Computing Systems.
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005
Proceedings of the 19th Annual International Conference on Supercomputing, 2005
Proceedings of the High Performance Embedded Architectures and Compilers, 2005
2004
Concurr. Comput. Pract. Exp., 2004
Towards a Systematic, Pragmatic and Architecture-Aware Program Optimization Process for Complex Processors.
Proceedings of the ACM/IEEE SC2004 Conference on High Performance Networking and Computing, 2004
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004
Proceedings of the Euro-Par 2004 Parallel Processing, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004
2003
DiST: a simple, reliable and scalable method to significantly reduce processor architecture simulation time.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2003
Proceedings of the Languages and Compilers for Parallel Computing, 2003
2002
J. Syst. Archit., 2002
Proceedings of the 2002 workshop on Computer architecture education, 2002
On increasing architecture awareness in program optimizations to bridge the gap between peak and sustained processor performance: matrix-multiply revisited.
Proceedings of the 2002 ACM/IEEE conference on Supercomputing, 2002
2000
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000
1999
ACM Trans. Comput. Syst., 1999
An Algorithm for Optimally Exploiting Spatial and Temporal Locality in Upper Memory Levels.
IEEE Trans. Computers, 1999
1998
Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998
Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998
1997
Proceedings of the 11th international conference on Supercomputing, 1997
1996
Proceedings of the 10th international conference on Supercomputing, 1996
Proceedings of the ASPLOS-VII Proceedings, 1996
1995
Influence of Cross-Interferences on Blocked Loops: A Case Study with Matric-Vector Multiply
ACM Trans. Program. Lang. Syst., 1995
1994
Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1994
Proceedings of the 8th international conference on Supercomputing, 1994
1993
To copy or not to copy: a compile-time technique for assessing when data copying should be used to eliminate cache conflicts.
Proceedings of the Proceedings Supercomputing '93, 1993
Proceedings of the 7th international conference on Supercomputing, 1993
Proceedings of the 1993 International Conference on Parallel Processing, 1993
Fast Enumeration of Solutions for Data Dependence Analysis and Data Locality Optimization.
Proceedings of the 1993 International Conference on Parallel Processing, 1993
1992
Proceedings of the Proceedings Supercomputing '92, 1992