Olivier Sentieys

Sharad Sinha

ACM Trans. Embed. Comput. Syst., November, 2024

Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe).

[BibT_eX]

[DOI]

Pavitra Prakash Bhade

Joseph Paturel

Sharad Sinha

ACM Trans. Embed. Comput. Syst., July, 2024

A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories.

[BibT_eX]

[DOI]

Léo De La Fuente

Jean-Frédéric Christmann

Manuel Pezzin

Matthias Remars

Josie E. Rodriguez Condia

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Reliability and Security of AI Hardware.

[BibT_eX]

[DOI]

Annachiara Ruospo

Ernesto Sánchez

Proceedings of the IEEE European Test Symposium, 2024

A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training.

[BibT_eX]

[DOI]

Sami Ben Ali

Silviu-Ioan Filip

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Cross-Layer Reliability Evaluation and Efficient Hardening of Large Vision Transformers Models.

[BibT_eX]

[DOI]

Lucas Roquet

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Characterizing and Modeling Synchronous Clock-Glitch Fault Injection.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024

FPGA-based CNN Acceleration using Pattern-Aware Pruning.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

AdaQAT: Adaptive Bit-Width Quantization-Aware Training.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Lossless Neural Network Model Compression Through Exponent Sharing.

[BibT_eX]

[DOI]

Prachi Kashikar

Sharad Sinha

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Approximation-Aware Task Deployment on Heterogeneous Multicore Platforms With DVFS.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Low-Precision Floating-Point for Efficient On-Board Deep Neural Network Processing.

[BibT_eX]

[DOI]

CoRR, 2023

harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs.

[BibT_eX]

[DOI]

Pegdwende Romaric Nikiema

Proceedings of the IEEE European Test Symposium, 2023

Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead.

[BibT_eX]

[DOI]

Pegdwende Romaric Nikiema

Proceedings of the 35th Euromicro Conference on Real-Time Systems, 2023

Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

A machine-learning-guided framework for fault-tolerant DNNs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Maximizing Computing Accuracy on Resource-Constrained Architectures.

[BibT_eX]

[DOI]

Van-Phu Ha

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

When Side-Channel Attacks Break the Black-Box Property of Embedded Artificial Intelligence.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Workshop on Artificial Intelligence and Security, 2023

2022

Dynamic fault-tolerant VLIW processor with heterogeneous Function Units.

[BibT_eX]

[DOI]

Microprocess. Microsystems, September, 2022

Approximations in Deep Learning.

[BibT_eX]

[DOI]

CoRR, 2022

Customizing Number Representation and Precision.

[BibT_eX]

[DOI]

CoRR, 2022

Characterizing a Neutron-Induced Fault Model for Deep Neural Networks.

[BibT_eX]

[DOI]

Josie Esteban Rodriguez Condia

Juan-David Guerrero-Balaguera

Matteo Sonza Reorda

Paolo Rech

CoRR, 2022

Evaluating the Impact of Mixed-Precision on Fault Propagation for Deep Neural Networks on GPUs.

[BibT_eX]

[DOI]

Paolo Rech

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Experimental evaluation of neutron-induced errors on a multicore RISC-V platform.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Functional and Timing Implications of Transient Faults in Critical Systems.

[BibT_eX]

[DOI]

Panagiota Nikolaou

Ivan Rodriguez-Ferrandez

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

Flodam: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs.

[BibT_eX]

[DOI]

Patrice Deroux-Dauphin

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Disentangled Loss for Low-Bit Quantization-Aware Training.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022

2021

Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems.

[BibT_eX]

[DOI]

Davide Pala

Ivan Miro-Panades

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Real-Time Imprecise Computation Tasks Mapping for DVFS-Enabled Networked Systems.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2021

Binary Tree Classification of Rigid Error Detection and Correction Techniques.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2021

AdequateDL: Approximating Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Leveraging Bayesian Optimization to Speed Up Automatic Precision Tuning.

[BibT_eX]

[DOI]

Van-Phu Ha

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures.

[BibT_eX]

[DOI]

Baptiste Roux

Jean-Philippe Delahaye

Microprocess. Microsystems, 2020

Fast Cross-Layer Vulnerability Analysis of Complex Hardware Designs.

[BibT_eX]

[DOI]

Joseph Paturel

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Towards Generic and Scalable Word-Length Optimization.

[BibT_eX]

[DOI]

Van-Phu Ha

Tomofumi Yuki

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Improving NILM by Combining Sensor Data and Linear Programming.

[BibT_eX]

[DOI]

Nicolas Roux

Baptiste Vrigneau

Proceedings of the IEEE Sensors Applications Symposium, 2019

Multi-carrier spread-spectrum transceiver for WiNoC.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Adaptive Transceiver for Wireless NoC to Enhance Multicast/Unicast Communication Scenarios.

[BibT_eX]

[DOI]

Joel Ortiz Sosa

Christian Roland

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Approximation-aware Task Deployment on Asymmetric Multicore Processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Accelerating Itemset Sampling using Satisfiability Constraints on FPGA.

[BibT_eX]

[DOI]

Mael Gueguen

Alexandre Termier

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors.

[BibT_eX]

[DOI]

Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019

Error Analysis of the Square Root Operation for the Purpose of Precision Tuning: A Case Study on K-means.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

Energy-Quality-Time Optimized Task Mapping on DVFS-Enabled Multicores.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

New metric for <i>IQ</i> imbalance compensation in optical QPSK coherent systems.

[BibT_eX]

[DOI]

Photonic Netw. Commun., 2018

Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

Controllable QoS for Imprecise Computation Tasks on DVFS Multicores With Time and Energy Constraints.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment.

[BibT_eX]

[DOI]

Joel Ortiz Sosa

Christian Roland

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Zyggie: A Wireless Body Area Network platform for indoor positioning and motion tracking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Run-Time management of energy-performance trade-off in Optical Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017

Blind Transmitter IQ Imbalance Compensation in M-QAM Optical Coherent Systems.

[BibT_eX]

[DOI]

JOCN, 2017

Customizing fixed-point and floating-point arithmetic - A case study in K-means clustering.

[BibT_eX]

[DOI]

Benjamin Barrois

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Implications of Reduced-Precision Computations in HPC: Performance, Energy and Error.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing is Everywhere, 2017

Run-time Instruction Replication for permanent and soft error mitigation in VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Taking advantage of correlation in stochastic computing.

[BibT_eX]

[DOI]

Rahul Kumar Budhwani

Rengarajan Ragavan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Evaluation of NoC on multi-FPGA interconnection using GTX transceiver.

[BibT_eX]

[DOI]

Atef Dorai

Hélène Dubois

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Decomposed Task Mapping to Maximize QoS in Energy-Constrained Real-Time Multicores.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Fast and Energy-Driven Design Space Exploration for Heterogeneous Architectures.

[BibT_eX]

[DOI]

Baptiste Roux

Jean-Philippe Delahaye

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Pushing the limits of voltage over-scaling for error-resilient applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

The hidden cost of functional approximation against careful data sizing - A case study.

[BibT_eX]

[DOI]

Benjamin Barrois

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2016

A Heuristic Self-Adaptive Medium Access Control for Resource-Constrained WBAN Systems.

[BibT_eX]

[DOI]

IEEE Access, 2016

Bi-harmonic decomposition-based maximum loglikelihood estimator for carrier phase estimation of coherent optical M-QAM.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window.

[BibT_eX]

[DOI]

Rengarajan Ragavan

Cédric Killian

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Blind adaptive transmitter IQ imbalance compensation in M-QAM optical coherent systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Communications, 2016

Effects of I/O routing through column interfaces in embedded FPGA fabrics.

[BibT_eX]

[DOI]

Russell Tessier

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Leveraging power spectral density for scalable system-level accuracy evaluation.

[BibT_eX]

[DOI]

Benjamin Barrois

Karthick Parashar

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Energy-Neutral Design Framework for Supercapacitor-Based Autonomous Wireless Sensor Networks.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

Designing applications for heterogeneous many-core architectures with the FlexTiles Platform.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

l1-Norm minimization based algorithm for non-intrusive load monitoring.

[BibT_eX]

[DOI]

Xuan-Chien Le

Baptiste Vrigneau

Proceedings of the 2015 IEEE International Conference on Pervasive Computing and Communication Workshops, 2015

Nonlinear phase noise reduction for 20-Gbit/s NRZ-QPSK signals using InP on SOI photonic crystal nanocavity.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

Low complexity on-chip distributed DC-DC converter for low power WSN nodes.

[BibT_eX]

[DOI]

Rengarajan Ragavan

Cédric Killian

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Communication Aware Design Method for Optical Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Energy-Aware Computing via Adaptive Precision under Performance Constraints in OFDM Wireless Receivers.

[BibT_eX]

[DOI]

Fernando Cladera Ojeda

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Radio signature based posture recognition using WBSN.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Information Processing in Sensor Networks, 2015

Joint simple blind IQ imbalance compensation and adaptive equalization for 16-QAM optical communications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Communications, 2015

Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

Channel-aware energy optimization of OFDM receivers using dynamic precision scaling in FPGAS.

[BibT_eX]

[DOI]

Fernando Cladera Ojeda

Proceedings of the 23rd European Signal Processing Conference, 2015

Design flow and run-time management for compressed FPGA configurations.

[BibT_eX]

[DOI]

Antoine Courtay

Karthick Nagaraj Parashar

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Low-complexity energy proportional posture/gesture recognition based on WBSN.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2015

2014

Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth Operations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Design of the coarse-grained reconfigurable architecture DART with on-line error detection.

[BibT_eX]

[DOI]

Syed M. A. H. Jafri

Microprocess. Microsystems, 2014

Power consumption models for the use of dynamic and partial reconfiguration.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

A frame-based domain-specific language for rapid prototyping of FPGA-based software-defined radios.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2014

RIC-MAC: A MAC protocol for low-power cooperative wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

A power manager with balanced quality of service for energy-harvesting wireless sensor nodes.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Energy Neutral Sensing Systems, 2014

IQ imbalance compensation based on maximum SNR estimation in coherent QPSK systems.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Transparent Optical Networks, 2014

Toward scalable source level accuracy analysis for floating-point to fixed-point conversion.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

FPGA architecture support for heterogeneous, relocatable partial bitstreams.

[BibT_eX]

[DOI]

Russell Tessier

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions.

[BibT_eX]

[DOI]

Russell Tessier

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Design Space Exploration in an FPGA-Based Software Defined Radio.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Frame-based modeling for automatic synthesis of FPGA-Software Defined Radio.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2014

2013

Évaluation de la précision en virgule fixe dans le cas des structures conditionnelles.

[BibT_eX]

[DOI]

Jean-Charles Naud

Tech. Sci. Informatiques, 2013

Compiling Scilab to high performance embedded multicore systems.

[BibT_eX]

[DOI]

Grigoris Dimitroulakos

Kostas Masselos

Dimitrios Kritharidis

Nikolaos Mitas

Thomas Perschke

Microprocess. Microsystems, 2013

On the performance of distributed space-time coded cooperative relay networks based on inter-relay communications.

[BibT_eX]

[DOI]

EURASIP J. Wirel. Commun. Netw., 2013

A Novel Hierarchical Low Complexity Synchronization Method for OFDM Systems.

[BibT_eX]

[DOI]

Pramod P. Udupa

Pascal Scalart

Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

An FPGA Software Defined Radio Platform with a High-Level Synthesis Design Flow.

[BibT_eX]

[DOI]

Vaibhav Bhatnagar

Arnaud Carer

Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

Multi-source power manager for super-capacitor based energy harvesting WSN.

[BibT_eX]

[DOI]

Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

Ultra low power asynchronous MAC protocol using wake-up radio for energy neutral WSN.

[BibT_eX]

[DOI]

Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

GeCoS: A framework for prototyping custom hardware design flows.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Working Conference on Source Code Analysis and Manipulation, 2013

Energy efficient reservation-based opportunistic MAC scheme in multi-hop networks.

[BibT_eX]

[DOI]

Ruifeng Zhang

Proceedings of the 24th IEEE Annual International Symposium on Personal, 2013

Duty-cycle power manager for thermal-powered Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Personal, 2013

Power reconfigurable receiver model for energy-aware applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

HarvWSNet: A co-simulation framework for energy harvesting wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computing, Networking and Communications, 2013

A polynomial time algorithm for solving the word-length optimization problem.

[BibT_eX]

[DOI]

Karthick Parashar

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A block-parallel architecture for initial and fine synchronization in OFDM systems.

[BibT_eX]

[DOI]

Pramod P. Udupa

Pascal Scalart

Proceedings of IEEE International Conference on Communications, 2013

A low-latency and energy-efficient MAC protocol for cooperative wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Global Communications Conference, 2013

Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based Implementations.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Adaptive Filter for Energy Predictor in Energy Harvesting Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2013, 2013

Prototyping an Energy Harvesting Wireless Sensor Network Application Using HarvWSNet.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2013, 2013

On the Energy Savings of Adaptive Transmit Power for Wireless Sensor Networks Radio Transceivers.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2013, 2013

2012

System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow.

[BibT_eX]

[DOI]

Gabriel Marchesan Almeida

ACM Trans. Design Autom. Electr. Syst., 2012

Analytical Approach for Numerical Accuracy Estimation of Fixed-Point Systems Based on Smooth Operations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A Discrete Model for Correlation Between Quantization Noises.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

High-Level Synthesis under Fixed-Point Accuracy Constraint.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2012

TAD-MAC: Traffic-Aware Dynamic MAC Protocol for Wireless Body Area Sensor Networks.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Quantization of VLSI digital signal processing systems.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2012

Energy-delay tradeoff in wireless multihop networks with unreliable links.

[BibT_eX]

[DOI]

Ad Hoc Networks, 2012

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures.

[BibT_eX]

[DOI]

Fabrice Lemonnier

Philippe Millet

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

From Scilab to multicore embedded systems: Algorithms and methodologies.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Power consumption model for partial and dynamic reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Impact of RF front-end nonlinearity on WSN Communications.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

Power Manager with PID Controller in Energy Harvesting Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Green Computing and Communications, 2012

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.

[BibT_eX]

[DOI]

Dimitrios Kritharidis

Nikolaos Mitas

Diana Göhringer

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Design of fixed-point embedded systems (DEFIS) French ANR project.

[BibT_eX]

[DOI]

Laurent-Stéphane Didier

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

GRECO: GREen communicating objects.

[BibT_eX]

[DOI]

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

A semiempirical model for wakeup time estimation in power-gated logic clusters.

[BibT_eX]

[DOI]

Vivek D. Tovinakere

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Latency-Energy Optimized MAC Protocol for Body Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 Ninth International Conference on Wearable and Implantable Body Sensor Networks, 2012

2011

Energy-Efficient Cooperative Techniques for Infrastructure-to-Vehicle Communications.

[BibT_eX]

[DOI]

IEEE Trans. Intell. Transp. Syst., 2011

Parallelism Level Impact on Energy Consumption in Reconfigurable Devices.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2011

Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network.

[BibT_eX]

[DOI]

J. Syst. Archit., 2011

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters.

[BibT_eX]

[DOI]

Vivek D. Tovinakere

J. Low Power Electron., 2011

Lower Bound of Energy-Latency Tradeoff of Opportunistic Routing in Multihop Networks.

[BibT_eX]

[DOI]

EURASIP J. Wirel. Commun. Netw., 2011

A Hybrid Model for Accurate Energy Analysis of WSN Nodes.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2011

Non-regenerative full distributed space-time codes in cooperative relaying networks.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters.

[BibT_eX]

[DOI]

Vivek D. Tovinakere

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Towards a power and energy efficient use of partial dynamic reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Parallel Evaluation of Hopfield Neural Networks.

[BibT_eX]

Proceedings of the NCTA 2011, 2011

Novel algorithms for word-length optimization.

[BibT_eX]

[DOI]

Hai-Nam Nguyen

Proceedings of the 19th European Signal Processing Conference, 2011

Fixed-point accuracy evaluation in the context of conditional structures.

[BibT_eX]

[DOI]

Proceedings of the 19th European Signal Processing Conference, 2011

Error recovery technique for coarse-grained reconfigurable architectures.

[BibT_eX]

[DOI]

Muhammad Moazam Azeem

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Graphic rendering application profiling on a shared memory MPSOC architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Spectral efficiency and energy efficiency of distributed space-time relaying models.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Consumer Communications and Networking Conference, 2011

Accurate Energy Consumption Evaluation of Preamble Sampling MAC Protocols for WSN.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2011, 2011

2010

Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect.

[BibT_eX]

[DOI]

Jean-Marc Philippe

Microelectron. J., 2010

Spatial Switching Data Coding Technique Analysis and Improvements for Interconnect Power Consumption Optimization.

[BibT_eX]

[DOI]

Antoine Courtay

Johann Laurent

J. Low Power Electron., 2010

Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication".

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2010

Accuracy evaluation of fixed-point based LMS algorithm.

[BibT_eX]

[DOI]

Digit. Signal Process., 2010

Cooperative MISO and Relay Comparison in Energy Constrained WSNs.

[BibT_eX]

[DOI]

Proceedings of the 71st IEEE Vehicular Technology Conference, 2010

A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Design of a fault-tolerant coarse-grained.

[BibT_eX]

[DOI]

Syed M. A. H. Jafri

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Fast performance evaluation of fixed-point systems with un-smooth operators.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Analytical approach for analyzing quantization noise effects on decision operators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2010

Estimating frequency characteristics of quantization noise for performance evaluation of fixed point systems.

[BibT_eX]

[DOI]

Proceedings of the 18th European Signal Processing Conference, 2010

Quantization mode opportunities in fixed-point system design.

[BibT_eX]

[DOI]

Proceedings of the 18th European Signal Processing Conference, 2010

System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Task placement for dynamic and partial reconfigurable architecture.

[BibT_eX]

[DOI]

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design.

[BibT_eX]

[DOI]

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

PowWow : Power Optimized Hardware/Software Framework for Wireless Motes.

[BibT_eX]

[DOI]

Proceedings of the ARCS '10, 2010

2009

On-the-Fly Evaluation of FPGA-Based True Random Number Generator.

[BibT_eX]

[DOI]

Renaud Santoro

Sébastien Roy

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

On-line Monitoring of Random Number Generators for Embedded Security.

[BibT_eX]

[DOI]

Renaud Santoro

Sébastien Roy

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Ultra Low-power FSM for Control Oriented Applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Dynamic Precision Scaling for Low Power WCDMA Receiver.

[BibT_eX]

[DOI]

Hai-Nam Nguyen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Minimum Distance Based Precoder for MIMO-OFDM Systems Using a 16-QAM Modulation.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2009

Design of optimized fixed-point WCDMA receiver.

[BibT_eX]

[DOI]

Hai-Nam Nguyen

Proceedings of the 17th European Signal Processing Conference, 2009

xMAML: A Modeling Language for Dynamically Reconfigurable Architectures.

[BibT_eX]

[DOI]

Julien Lallet

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Reconfigurable Operator Based Multimedia Embedded Processor.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

Structure mémoire reconfigurable. Vers une structure de stockage faible consommation.

[BibT_eX]

[DOI]

Tech. Sci. Informatiques, 2008

Analytical Fixed-Point Accuracy Evaluation in Linear Time-Invariant Systems.

[BibT_eX]

[DOI]

Romuald Rocher

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

High-Level Interconnect Delay and Power Estimation.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency.

[BibT_eX]

[DOI]

Raphaël David

EURASIP J. Embed. Syst., 2008

Accuracy Constraint Determination in Fixed-Point System Design.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2008

Efficient Space Time Combination Technique for Unsynchronized Cooperative Miso Transmission.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

Efficient dynamic reconfiguration for multi-context embedded FPGA.

[BibT_eX]

[DOI]

Julien Lallet

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Impact of Transmission Synchronization Error and Cooperative Reception Techniques on the Performance of Cooperative MIMO Systems.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2008

Bit accurate roundoff noise analysis of fixed-point linear controllers.

[BibT_eX]

[DOI]

Thibault Hilaire

Proceedings of the IEEE International Conference on Computer-Aided Control Systems, 2008

2007

Cooperative MIMO Schemes Optimal Selection for Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2007

Analytical accuracy evaluation of fixed-point systems.

[BibT_eX]

[DOI]

Proceedings of the 15th European Signal Processing Conference, 2007

Roundoff noise analysis of finite wordlength realizations with the implicit state-space framework.

[BibT_eX]

[DOI]

Thibault Hilaire

Proceedings of the 15th European Signal Processing Conference, 2007

Hardware task scheduling for heterogeneous soc architectures.

[BibT_eX]

[DOI]

Proceedings of the 15th European Signal Processing Conference, 2007

Modeling of Interconnection Networks in Massively Parallel Processor Architectures.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems, 2007

About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations.

[BibT_eX]

[DOI]

Nicolas Hervé

Proceedings of the Reconfigurable Computing: Architectures, 2007

2006

Fixed-Point Configurable Hardware Components.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2006

Floating-to-Fixed-Point Conversion for Digital Signal Processors.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2006

Control Unit for Parallel Embedded System.

[BibT_eX]

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects.

[BibT_eX]

[DOI]

Jean-Marc Philippe

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Fixed-point configurable hardware components for adaptive filters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An energy-efficient ternary interconnection link for asynchronous systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Co-Design of Massively Parallel Embedded Processor Architectures.

[BibT_eX]

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

A low-power and high-speed quaternary interconnection link using efficient converters.

[BibT_eX]

[DOI]

Jean-Marc Philippe

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Accuracy evaluation of fixed-point APA algorithm [adaptive filter applications].

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2004

DSP Code Generation with Optimized Data Word-Length Selection.

[BibT_eX]

[DOI]

Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Compiler and System Techniques for soc Distributed Reconfigurable Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Accuracy evaluation of fixed-point LMS algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Automatic SQNR determination in non-linear and non-recursive fixed-point systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 12th European Signal Processing Conference, 2004

2003

Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe.

[BibT_eX]

[DOI]

Tech. Sci. Informatiques, 2003

MVL circuit design and characterization at the transistor level using SUS-LOC.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2002

Behavioral IP Specification and Integration Framework for High-Level Design Reuse.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints.

[BibT_eX]

[DOI]

Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

A methodology for evaluating the precision of fixed-point systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2002

Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2002

A Compilation Framework for a Dynamically Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

Influence of fixed-point DSP architecture on computation accuracy.

[BibT_eX]

[DOI]

Philippe Quemerais

Proceedings of the 11th European Signal Processing Conference, 2002

Automatic Evaluation of the Accuracy of Fixed-Point Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Automatic floating-point to fixed-point conversion for DSP code generation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2002

2001

A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.

[BibT_eX]

Proceedings of the SOC Design Methodologies, 2001

2000

A Framework for High Level Estimations of Signal Processing VLSI Implementations.

[BibT_eX]

[DOI]

Jean-Philippe Diguet

J. VLSI Signal Process., 2000

Teaching hardware/software system codesign using CAD tools: a case study in image synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Educ., 2000

Multi-algorithm ASIP synthesis and power estimation for DSP applications.

[BibT_eX]

[DOI]

Jean-Gabriel Cousin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Behavioral synthesis of asynchronous systems: a methodology.

[BibT_eX]

[DOI]

J. O. Dedou

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Memory Unit Design for Real Time DSP Applications.

[BibT_eX]

[DOI]

Michel Corazza

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

VLSI implementation and complexity comparison of residue generators modulo 3.

[BibT_eX]

[DOI]

Fabrice Pedron

Proceedings of the 9th European Signal Processing Conference, 1998

Asynchronous timing model for high-level synthesis of DSP applications.

[BibT_eX]

[DOI]

J. Okito Dedou