Olivier Sentieys

Orcid: 0000-0003-4334-6418

According to our database1, Olivier Sentieys authored at least 233 papers between 1993 and 2024.

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Bibliography

2024
Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression.
ACM Trans. Embed. Comput. Syst., November, 2024

Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe).
ACM Trans. Embed. Comput. Syst., July, 2024

A Hard-Label Cryptanalytic Extraction of Non-Fully Connected Deep Neural Networks using Side-Channel Attacks.
IACR Cryptol. ePrint Arch., 2024

A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024


A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Cross-Layer Reliability Evaluation and Efficient Hardening of Large Vision Transformers Models.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Characterizing and Modeling Synchronous Clock-Glitch Fault Injection.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024

Efficient Neural Networks: from SW optimization to specialized HW accelerators.
Proceedings of the International Conference on Compilers, 2024

FPGA-based CNN Acceleration using Pattern-Aware Pruning.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

AdaQAT: Adaptive Bit-Width Quantization-Aware Training.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
Lossless Neural Network Model Compression Through Exponent Sharing.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Approximation-Aware Task Deployment on Heterogeneous Multicore Platforms With DVFS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Low-Precision Floating-Point for Efficient On-Board Deep Neural Network Processing.
CoRR, 2023

harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs.
Proceedings of the IEEE European Test Symposium, 2023

Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead.
Proceedings of the 35th Euromicro Conference on Real-Time Systems, 2023

Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

A machine-learning-guided framework for fault-tolerant DNNs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Maximizing Computing Accuracy on Resource-Constrained Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

When Side-Channel Attacks Break the Black-Box Property of Embedded Artificial Intelligence.
Proceedings of the 16th ACM Workshop on Artificial Intelligence and Security, 2023

2022
Dynamic fault-tolerant VLIW processor with heterogeneous Function Units.
Microprocess. Microsystems, September, 2022

Approximations in Deep Learning.
CoRR, 2022

Customizing Number Representation and Precision.
CoRR, 2022

Characterizing a Neutron-Induced Fault Model for Deep Neural Networks.
CoRR, 2022

Evaluating the Impact of Mixed-Precision on Fault Propagation for Deep Neural Networks on GPUs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Experimental evaluation of neutron-induced errors on a multicore RISC-V platform.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Functional and Timing Implications of Transient Faults in Critical Systems.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training.
Proceedings of the International Conference on Field-Programmable Technology, 2022

Flodam: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Disentangled Loss for Low-Bit Quantization-Aware Training.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022

2021
Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Real-Time Imprecise Computation Tasks Mapping for DVFS-Enabled Networked Systems.
IEEE Internet Things J., 2021

Binary Tree Classification of Rigid Error Detection and Correction Techniques.
ACM Comput. Surv., 2021

AdequateDL: Approximating Deep Learning Accelerators.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Leveraging Bayesian Optimization to Speed Up Automatic Precision Tuning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures.
Microprocess. Microsystems, 2020

Fast Cross-Layer Vulnerability Analysis of Complex Hardware Designs.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Towards Generic and Scalable Word-Length Optimization.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Improving NILM by Combining Sensor Data and Linear Programming.
Proceedings of the IEEE Sensors Applications Symposium, 2019

Multi-carrier spread-spectrum transceiver for WiNoC.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Adaptive Transceiver for Wireless NoC to Enhance Multicast/Unicast Communication Scenarios.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications.
Proceedings of the International Conference on Computer-Aided Design, 2019

Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Approximation-aware Task Deployment on Asymmetric Multicore Processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Accelerating Itemset Sampling using Satisfiability Constraints on FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors.
Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019

Error Analysis of the Square Root Operation for the Purpose of Precision Tuning: A Case Study on K-means.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Energy-Quality-Time Optimized Task Mapping on DVFS-Enabled Multicores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

New metric for <i>IQ</i> imbalance compensation in optical QPSK coherent systems.
Photonic Netw. Commun., 2018

Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects.
ACM J. Emerg. Technol. Comput. Syst., 2018

Controllable QoS for Imprecise Computation Tasks on DVFS Multicores With Time and Energy Constraints.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Zyggie: A Wireless Body Area Network platform for indoor positioning and motion tracking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Run-Time management of energy-performance trade-off in Optical Network-on-Chip.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Blind Transmitter IQ Imbalance Compensation in M-QAM Optical Coherent Systems.
JOCN, 2017

Customizing fixed-point and floating-point arithmetic - A case study in K-means clustering.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Implications of Reduced-Precision Computations in HPC: Performance, Energy and Error.
Proceedings of the Parallel Computing is Everywhere, 2017

Run-time Instruction Replication for permanent and soft error mitigation in VLIW processors.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Taking advantage of correlation in stochastic computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Evaluation of NoC on multi-FPGA interconnection using GTX transceiver.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Decomposed Task Mapping to Maximize QoS in Energy-Constrained Real-Time Multicores.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Fast and Energy-Driven Design Space Exploration for Heterogeneous Architectures.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Pushing the limits of voltage over-scaling for error-resilient applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

The hidden cost of functional approximation against careful data sizing - A case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems.
J. Low Power Electron., 2016

A Heuristic Self-Adaptive Medium Access Control for Resource-Constrained WBAN Systems.
IEEE Access, 2016

Bi-harmonic decomposition-based maximum loglikelihood estimator for carrier phase estimation of coherent optical M-QAM.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Blind adaptive transmitter IQ imbalance compensation in M-QAM optical coherent systems.
Proceedings of the 2016 IEEE International Conference on Communications, 2016

Effects of I/O routing through column interfaces in embedded FPGA fabrics.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Leveraging power spectral density for scalable system-level accuracy evaluation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Energy-Neutral Design Framework for Supercapacitor-Based Autonomous Wireless Sensor Networks.
ACM J. Emerg. Technol. Comput. Syst., 2015

Designing applications for heterogeneous many-core architectures with the FlexTiles Platform.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

l1-Norm minimization based algorithm for non-intrusive load monitoring.
Proceedings of the 2015 IEEE International Conference on Pervasive Computing and Communication Workshops, 2015

Nonlinear phase noise reduction for 20-Gbit/s NRZ-QPSK signals using InP on SOI photonic crystal nanocavity.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

Low complexity on-chip distributed DC-DC converter for low power WSN nodes.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Communication Aware Design Method for Optical Network-on-Chip.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Energy-Aware Computing via Adaptive Precision under Performance Constraints in OFDM Wireless Receivers.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Radio signature based posture recognition using WBSN.
Proceedings of the 14th International Conference on Information Processing in Sensor Networks, 2015

Joint simple blind IQ imbalance compensation and adaptive equalization for 16-QAM optical communications.
Proceedings of the 2015 IEEE International Conference on Communications, 2015

Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

Channel-aware energy optimization of OFDM receivers using dynamic precision scaling in FPGAS.
Proceedings of the 23rd European Signal Processing Conference, 2015

Design flow and run-time management for compressed FPGA configurations.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Low-complexity energy proportional posture/gesture recognition based on WBSN.
Proceedings of the 12th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2015

2014
Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth Operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Design of the coarse-grained reconfigurable architecture DART with on-line error detection.
Microprocess. Microsystems, 2014

Power consumption models for the use of dynamic and partial reconfiguration.
Microprocess. Microsystems, 2014

A frame-based domain-specific language for rapid prototyping of FPGA-based software-defined radios.
EURASIP J. Adv. Signal Process., 2014

RIC-MAC: A MAC protocol for low-power cooperative wireless sensor networks.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

A power manager with balanced quality of service for energy-harvesting wireless sensor nodes.
Proceedings of the 2nd International Workshop on Energy Neutral Sensing Systems, 2014

IQ imbalance compensation based on maximum SNR estimation in coherent QPSK systems.
Proceedings of the 16th International Conference on Transparent Optical Networks, 2014

Toward scalable source level accuracy analysis for floating-point to fixed-point conversion.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

FPGA architecture support for heterogeneous, relocatable partial bitstreams.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Design Space Exploration in an FPGA-Based Software Defined Radio.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Frame-based modeling for automatic synthesis of FPGA-Software Defined Radio.
Proceedings of the 9th International Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2014

2013
Évaluation de la précision en virgule fixe dans le cas des structures conditionnelles.
Tech. Sci. Informatiques, 2013

Compiling Scilab to high performance embedded multicore systems.
Microprocess. Microsystems, 2013

On the performance of distributed space-time coded cooperative relay networks based on inter-relay communications.
EURASIP J. Wirel. Commun. Netw., 2013

A Novel Hierarchical Low Complexity Synchronization Method for OFDM Systems.
Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

An FPGA Software Defined Radio Platform with a High-Level Synthesis Design Flow.
Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

Multi-source power manager for super-capacitor based energy harvesting WSN.
Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

Ultra low power asynchronous MAC protocol using wake-up radio for energy neutral WSN.
Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

GeCoS: A framework for prototyping custom hardware design flows.
Proceedings of the 13th IEEE International Working Conference on Source Code Analysis and Manipulation, 2013

Energy efficient reservation-based opportunistic MAC scheme in multi-hop networks.
Proceedings of the 24th IEEE Annual International Symposium on Personal, 2013

Duty-cycle power manager for thermal-powered Wireless Sensor Networks.
Proceedings of the 24th IEEE Annual International Symposium on Personal, 2013

Power reconfigurable receiver model for energy-aware applications.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

HarvWSNet: A co-simulation framework for energy harvesting wireless sensor networks.
Proceedings of the International Conference on Computing, Networking and Communications, 2013

A polynomial time algorithm for solving the word-length optimization problem.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A block-parallel architecture for initial and fine synchronization in OFDM systems.
Proceedings of IEEE International Conference on Communications, 2013

A low-latency and energy-efficient MAC protocol for cooperative wireless sensor networks.
Proceedings of the 2013 IEEE Global Communications Conference, 2013

Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based Implementations.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Adaptive Filter for Energy Predictor in Energy Harvesting Wireless Sensor Networks.
Proceedings of the ARCS 2013, 2013

Prototyping an Energy Harvesting Wireless Sensor Network Application Using HarvWSNet.
Proceedings of the ARCS 2013, 2013

On the Energy Savings of Adaptive Transmit Power for Wireless Sensor Networks Radio Transceivers.
Proceedings of the ARCS 2013, 2013

2012
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow.
ACM Trans. Design Autom. Electr. Syst., 2012

Analytical Approach for Numerical Accuracy Estimation of Fixed-Point Systems Based on Smooth Operations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A Discrete Model for Correlation Between Quantization Noises.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

High-Level Synthesis under Fixed-Point Accuracy Constraint.
J. Electr. Comput. Eng., 2012

TAD-MAC: Traffic-Aware Dynamic MAC Protocol for Wireless Body Area Sensor Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Quantization of VLSI digital signal processing systems.
EURASIP J. Adv. Signal Process., 2012

Energy-delay tradeoff in wireless multihop networks with unreliable links.
Ad Hoc Networks, 2012

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012


A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Power consumption model for partial and dynamic reconfiguration.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Impact of RF front-end nonlinearity on WSN Communications.
Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

Power Manager with PID Controller in Energy Harvesting Wireless Sensor Networks.
Proceedings of the 2012 IEEE International Conference on Green Computing and Communications, 2012

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Design of fixed-point embedded systems (DEFIS) French ANR project.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012


A semiempirical model for wakeup time estimation in power-gated logic clusters.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Latency-Energy Optimized MAC Protocol for Body Sensor Networks.
Proceedings of the 2012 Ninth International Conference on Wearable and Implantable Body Sensor Networks, 2012

2011
Energy-Efficient Cooperative Techniques for Infrastructure-to-Vehicle Communications.
IEEE Trans. Intell. Transp. Syst., 2011

Parallelism Level Impact on Energy Consumption in Reconfigurable Devices.
SIGARCH Comput. Archit. News, 2011

Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network.
J. Syst. Archit., 2011

A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters.
J. Low Power Electron., 2011

Lower Bound of Energy-Latency Tradeoff of Opportunistic Routing in Multihop Networks.
EURASIP J. Wirel. Commun. Netw., 2011

A Hybrid Model for Accurate Energy Analysis of WSN Nodes.
EURASIP J. Embed. Syst., 2011

Non-regenerative full distributed space-time codes in cooperative relaying networks.
Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Towards a power and energy efficient use of partial dynamic reconfiguration.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Parallel Evaluation of Hopfield Neural Networks.
Proceedings of the NCTA 2011, 2011

Novel algorithms for word-length optimization.
Proceedings of the 19th European Signal Processing Conference, 2011

Fixed-point accuracy evaluation in the context of conditional structures.
Proceedings of the 19th European Signal Processing Conference, 2011

Error recovery technique for coarse-grained reconfigurable architectures.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Graphic rendering application profiling on a shared memory MPSOC architecture.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Spectral efficiency and energy efficiency of distributed space-time relaying models.
Proceedings of the 2011 IEEE Consumer Communications and Networking Conference, 2011

Accurate Energy Consumption Evaluation of Preamble Sampling MAC Protocols for WSN.
Proceedings of the ARCS 2011, 2011

2010
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect.
Microelectron. J., 2010

Spatial Switching Data Coding Technique Analysis and Improvements for Interconnect Power Consumption Optimization.
J. Low Power Electron., 2010

Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication".
IEEE Commun. Lett., 2010

Accuracy evaluation of fixed-point based LMS algorithm.
Digit. Signal Process., 2010

Cooperative MISO and Relay Comparison in Energy Constrained WSNs.
Proceedings of the 71st IEEE Vehicular Technology Conference, 2010

A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Design of a fault-tolerant coarse-grained.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Fast performance evaluation of fixed-point systems with un-smooth operators.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Analytical approach for analyzing quantization noise effects on decision operators.
Proceedings of the IEEE International Conference on Acoustics, 2010

Estimating frequency characteristics of quantization noise for performance evaluation of fixed point systems.
Proceedings of the 18th European Signal Processing Conference, 2010

Quantization mode opportunities in fixed-point system design.
Proceedings of the 18th European Signal Processing Conference, 2010

System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Task placement for dynamic and partial reconfigurable architecture.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking.
Proceedings of the 47th Design Automation Conference, 2010

PowWow : Power Optimized Hardware/Software Framework for Wireless Motes.
Proceedings of the ARCS '10, 2010

2009
On-the-Fly Evaluation of FPGA-Based True Random Number Generator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

On-line Monitoring of Random Number Generators for Embedded Security.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Ultra Low-power FSM for Control Oriented Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Dynamic Precision Scaling for Low Power WCDMA Receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Minimum Distance Based Precoder for MIMO-OFDM Systems Using a 16-QAM Modulation.
Proceedings of IEEE International Conference on Communications, 2009

Design of optimized fixed-point WCDMA receiver.
Proceedings of the 17th European Signal Processing Conference, 2009

xMAML: A Modeling Language for Dynamically Reconfigurable Architectures.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Reconfigurable Operator Based Multimedia Embedded Processor.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Structure mémoire reconfigurable. Vers une structure de stockage faible consommation.
Tech. Sci. Informatiques, 2008

Analytical Fixed-Point Accuracy Evaluation in Linear Time-Invariant Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

High-Level Interconnect Delay and Power Estimation.
J. Low Power Electron., 2008

DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency.
EURASIP J. Embed. Syst., 2008

Accuracy Constraint Determination in Fixed-Point System Design.
EURASIP J. Embed. Syst., 2008

Efficient Space Time Combination Technique for Unsynchronized Cooperative Miso Transmission.
Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

Efficient dynamic reconfiguration for multi-context embedded FPGA.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Impact of Transmission Synchronization Error and Cooperative Reception Techniques on the Performance of Cooperative MIMO Systems.
Proceedings of IEEE International Conference on Communications, 2008

Bit accurate roundoff noise analysis of fixed-point linear controllers.
Proceedings of the IEEE International Conference on Computer-Aided Control Systems, 2008

2007
Cooperative MIMO Schemes Optimal Selection for Wireless Sensor Networks.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures.
Proceedings of the International Joint Conference on Neural Networks, 2007

Analytical accuracy evaluation of fixed-point systems.
Proceedings of the 15th European Signal Processing Conference, 2007

Roundoff noise analysis of finite wordlength realizations with the implicit state-space framework.
Proceedings of the 15th European Signal Processing Conference, 2007

Hardware task scheduling for heterogeneous soc architectures.
Proceedings of the 15th European Signal Processing Conference, 2007

Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
Proceedings of the Architecture of Computing Systems, 2007

About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Fixed-Point Configurable Hardware Components.
EURASIP J. Embed. Syst., 2006

Floating-to-Fixed-Point Conversion for Digital Signal Processors.
EURASIP J. Adv. Signal Process., 2006

Control Unit for Parallel Embedded System.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Fixed-point configurable hardware components for adaptive filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An energy-efficient ternary interconnection link for asynchronous systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Co-Design of Massively Parallel Embedded Processor Architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

A low-power and high-speed quaternary interconnection link using efficient converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Accuracy evaluation of fixed-point APA algorithm [adaptive filter applications].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2004
DSP Code Generation with Optimized Data Word-Length Selection.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Compiler and System Techniques for soc Distributed Reconfigurable Accelerators.
Proceedings of the Computer Systems: Architectures, 2004

Accuracy evaluation of fixed-point LMS algorithm.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Automatic SQNR determination in non-linear and non-recursive fixed-point systems.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

2003
Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe.
Tech. Sci. Informatiques, 2003

MVL circuit design and characterization at the transistor level using SUS-LOC.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2002
Behavioral IP Specification and Integration Framework for High-Level Design Reuse.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

A methodology for evaluating the precision of fixed-point systems.
Proceedings of the IEEE International Conference on Acoustics, 2002

Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture.
Proceedings of the IEEE International Conference on Acoustics, 2002

A Compilation Framework for a Dynamically Reconfigurable Architecture.
Proceedings of the Field-Programmable Logic and Applications, 2002

Influence of fixed-point DSP architecture on computation accuracy.
Proceedings of the 11th European Signal Processing Conference, 2002

Automatic Evaluation of the Accuracy of Fixed-Point Algorithms.
Proceedings of the 2002 Design, 2002

Automatic floating-point to fixed-point conversion for DSP code generation.
Proceedings of the International Conference on Compilers, 2002

2001
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.
Proceedings of the SOC Design Methodologies, 2001

2000
A Framework for High Level Estimations of Signal Processing VLSI Implementations.
J. VLSI Signal Process., 2000

Teaching hardware/software system codesign using CAD tools: a case study in image synthesis.
IEEE Trans. Educ., 2000

Multi-algorithm ASIP synthesis and power estimation for DSP applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Behavioral synthesis of asynchronous systems: a methodology.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Memory Unit Design for Real Time DSP Applications.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
VLSI implementation and complexity comparison of residue generators modulo 3.
Proceedings of the 9th European Signal Processing Conference, 1998

Asynchronous timing model for high-level synthesis of DSP applications.
Proceedings of the 9th European Signal Processing Conference, 1998

1997
VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996
Memory aspects in signal processing and HLS tool: Some results.
Proceedings of the 8th European Signal Processing Conference, 1996

1994
Towards a multi-formalism framework for architectural synthesis: the ASAR project.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
GAUT: An architectural synthesis tool for dedicated signal processors.
Proceedings of the European Design Automation Conference 1993, 1993


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