Olivier Muller

According to our database, Olivier Muller authored at least 27 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Graph Neural Network based Future Clinical Events Prediction from Invasive Coronary Angiography.

Xiaowu Sun, Theofilos Belmpas, Ortal Yona Senouf, Emmanuel Abbe, Pascal Frossard, Bernard De Bruyne, Olivier Muller, Stéphane Fournier, Thabo Mahendiran, Dorina Thanou

Proceedings of the IEEE International Symposium on Biomedical Imaging, 2024

2023

A Chisel Framework for Flexible Design Space Exploration through a Functional Approach.

Bruno Ferres, Olivier Muller, Frédéric Rousseau

ACM Trans. Design Autom. Electr. Syst., July, 2023

Can Knowledge Transfer Techniques Compensate for the Limited Myocardial Infarction Data by Leveraging Hæmodynamics? An in silico Study.

Riccardo Tenderini, Federico Betti, Ortal Yona Senouf, Olivier Muller, Simone Deparis, Annalisa Buffa, Emmanuel Abbe

Proceedings of the Artificial Intelligence in Medicine, 2023

2022

Toward Agile Hardware Designs With Chisel: A Network Use Case.

Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot

IEEE Des. Test, 2022

2021

Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams.

Arif Sasongko, I. M. Narendra Kumara, Arief Wicaksana, Frédéric Rousseau, Olivier Muller

ACM Trans. Reconfigurable Technol. Syst., 2021

Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration.

Bruno Ferres, Olivier Muller, Frédéric Rousseau

Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021

2020

(System)Verilog to Chisel Translation for Faster Hardware Design.

Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot

Proceedings of the International Workshop on Rapid System Prototyping, 2020

Chisel Usecase: Designing General Matrix Multiply for FPGA.

Bruno Ferres, Olivier Muller, Frédéric Rousseau

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019

Efficient Decompression of Binary Encoded Balanced Ternary Sequences.

Olivier Muller, Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

Message-Oriented Devices on FPGAs.

Thomas Baumela, Olivier Gruber, Olivier Muller, Frédéric Pétrot

Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

An FPGA target for the StarPU heterogeneous runtime system.

Georgios Christodoulis, François Broquedis, Olivier Muller, Manuel Selva, Frederic Desprez

Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

2017

Prototyping dynamic task migration on heterogeneous reconfigurable systems.

Arief Wicaksana, Alban Bourge, Olivier Muller, Arif Sasongko, Frédéric Rousseau

Proceedings of the International Symposium on Rapid System Prototyping, 2017

2016

Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow.

Alban Bourge, Olivier Muller, Frédéric Rousseau

ACM Trans. Reconfigurable Technol. Syst., 2016

On-board non-regression test of HLS tools targeting FPGA.

Arief Wicaksana, Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau, Arif Sasongko

Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

Demonstration of a context-switch method for heterogeneous reconfigurable systems.

Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic.

Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Régis Leveugle, Frédéric Rousseau

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

A Novel Method for Enabling FPGA Context-Switch (Abstract Only).

Alban Bourge, Olivier Muller, Frédéric Rousseau

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems.

Alban Bourge, Olivier Muller, Frédéric Rousseau

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014

Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints.

Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau

J. Syst. Archit., 2014

2013

A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints.

Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

HCM: An abstraction layer for seamless programming of DPR FPGA.

Yan Xu, Olivier Muller, Pierre-Henri Horrein, Frédéric Pétrot

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2010

Parallelism Efficiency in Convolutional Turbo Decoding.

Olivier Muller, Amer Baghdadi, Michel Jézéquel

EURASIP J. Adv. Signal Process., 2010

2009

From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding.

Olivier Muller, Amer Baghdadi, Michel Jézéquel

IEEE Trans. Very Large Scale Integr. Syst., 2009

2008

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding.

Olivier Muller, Amer Baghdadi, Michel Jézéquel

Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

2007

Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding.

Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference.

Olivier Muller, Amer Baghdadi, Michel Jézéquel

Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.

Olivier Muller, Amer Baghdadi, Michel Jézéquel

Proceedings of the Conference on Design, Automation and Test in Europe, 2006