Olivier Muller

Orcid: 0000-0002-4182-0502

According to our database1, Olivier Muller authored at least 27 papers between 2006 and 2024.

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Bibliography

2024
Graph Neural Network based Future Clinical Events Prediction from Invasive Coronary Angiography.
Proceedings of the IEEE International Symposium on Biomedical Imaging, 2024

2023
A Chisel Framework for Flexible Design Space Exploration through a Functional Approach.
ACM Trans. Design Autom. Electr. Syst., July, 2023

Can Knowledge Transfer Techniques Compensate for the Limited Myocardial Infarction Data by Leveraging Hæmodynamics? An in silico Study.
Proceedings of the Artificial Intelligence in Medicine, 2023

2022
Toward Agile Hardware Designs With Chisel: A Network Use Case.
IEEE Des. Test, 2022

2021
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams.
ACM Trans. Reconfigurable Technol. Syst., 2021

Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration.
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021

2020
(System)Verilog to Chisel Translation for Faster Hardware Design.
Proceedings of the International Workshop on Rapid System Prototyping, 2020

Chisel Usecase: Designing General Matrix Multiply for FPGA.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
Efficient Decompression of Binary Encoded Balanced Ternary Sequences.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
Message-Oriented Devices on FPGAs.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

An FPGA target for the StarPU heterogeneous runtime system.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

2017
Prototyping dynamic task migration on heterogeneous reconfigurable systems.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

2016
Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow.
ACM Trans. Reconfigurable Technol. Syst., 2016

On-board non-regression test of HLS tools targeting FPGA.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

Demonstration of a context-switch method for heterogeneous reconfigurable systems.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
A Novel Method for Enabling FPGA Context-Switch (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints.
J. Syst. Archit., 2014

2013
A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
HCM: An abstraction layer for seamless programming of DPR FPGA.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2010
Parallelism Efficiency in Convolutional Turbo Decoding.
EURASIP J. Adv. Signal Process., 2010

2009
From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

2007
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006


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