Olivier Héron
According to our database1,
Olivier Héron
authored at least 25 papers
between 2003 and 2023.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Proceedings of the 12th International Symposium on Information and Communication Technology, 2023
2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
2017
Early estimation of aging in the design flow of integrated circuits through a programmable hardware module.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
2015
Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
2013
J. Electron. Test., 2013
When processors get old: Evaluation of BTI and HCI effects on performance and reliability.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2012
J. Low Power Electron., 2012
Relation between HCI-induced performance degradation and applications in a RISC processor.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
A Lightweight API for an Adaptive Software Fault Tolerance Using POSIX-Thread Replication.
Proceedings of the ARCS 2011, 2011
Impact of power management on temperature and reliability evolution for an embedded many-core architecture.
Proceedings of the ARCS 2011, 2011
2010
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010
Analysis of on-line self-testing policies for real-time embedded multiprocessors in DSM technologies.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
2006
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.
J. Electron. Test., 2006
2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs.
Proceedings of the 9th European Test Symposium, 2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 8th European Test Workshop, 2003