Olivier Faynot
Orcid: 0000-0002-5087-5484
According to our database1,
Olivier Faynot
authored at least 20 papers
between 2009 and 2024.
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Bibliography
2024
Experimental Decomposition of the Carrier Mobility in the Conduction Planes of 2-Level Stacked Nanowires.
Proceedings of the 21st International Conference on Electrical Engineering, 2024
2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
2018
Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2017
Microelectron. Reliab., 2017
2016
Microelectron. Reliab., 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Performance and reliability of strained SOI transistors for advanced planar FDSOI technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model.
Proceedings of the 45th European Solid State Device Research Conference, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations.
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Deep-amorphization and solid-phase epitaxial regrowth processes for hybrid orientation technologies in SOI MOSFETs with thin body.
Microelectron. Reliab., 2012
Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below.
J. Low Power Electron., 2012
Multibranch mobility characterization: Evidence of carrier mobility enhancement by back-gate biasing in FD-SOI MOSFET.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2009
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below.
Proceedings of the 35th European Solid-State Circuits Conference, 2009