Olivier Coudert

Proceedings of the 47th Design Automation Conference, 2010

2002

Timing and Design Closure in Physical Design Flows (invited).

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Optimization in an Integrated Physical Design Flow (Tutorial Abstract).

[BibT_eX]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001

Automatic Hierarchical Design: Fantasy or Reality? (Panel).

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

Incremental CAD.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Web-based frameworks to enable CAD RD (abstract).

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Timing closure: the solution and its problems.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1998

A Performance Study of BDD-Based Model Checking.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 1998

A New Paradigm for Dichotomy-based Constrained Encoding.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

Gate sizing for constrained delay/power/area optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

Solving graph optimization problems with ZBDDs.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

Exact Coloring of Real-Life Graphs is Easy.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

What is the state of the art in commercial EDA tools for low power?

[BibT_eX]

[DOI]

Kurt Keutzer

Ramsey W. Haddad

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Integrated resynthesis for low power.

[BibT_eX]

[DOI]

Ramsey W. Haddad

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Exact Dichotomy-based Constrained Encodi.

[BibT_eX]

[DOI]

C.-J. Richard Shi

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Gate Sizing: A General Purpose Optimization Approach.

[BibT_eX]

[DOI]

Proceedings of the 1996 European Design and Test Conference, 1996

New Algorithms for Gate Sizing: A Comparative Study.

[BibT_eX]

[DOI]

Ramsey W. Haddad

Srilatha Manne

Proceedings of the 33st Conference on Design Automation, 1996

On Solving Covering Problems.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

The Implicit Set Paradigm: A New Approach to Finite State System Verification.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1995

Doing Two-Level Logic Minimization 100 Times Faster.

[BibT_eX]

[DOI]

Proceedings of the Sixth Annual ACM-SIAM Symposium on Discrete Algorithms, 1995

New Ideas for Solving Covering Problems.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1994

Une approche intentionnelle du calcul des implicants premiers et essentiels des fonctions booléennes.

[BibT_eX]

[DOI]

RAIRO Theor. Informatics Appl., 1994

Two-level logic minimization: an overview.

[BibT_eX]

[DOI]

Integr., 1994

1993

Towards a Symbolic Logic Minimization Algorithm.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

A New Viewpoint on Two-Level Logic Minimization.

[BibT_eX]

[DOI]

Henri Fraisse

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Symbolic Prime Generation for Multiple-Valued Functions.

[BibT_eX]

[DOI]

Bill Lin

Proceedings of the 29th Design Automation Conference, 1992

Implicit and Incremental Computation of Primes and Essential Primes of Boolean Functions.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

A Logically Complete Reasoning Maintenance System Based on a Logical Constraint Solver.

[BibT_eX]

[DOI]

Proceedings of the 12th International Joint Conference on Artificial Intelligence. Sydney, 1991

1990

New ideas on symbolic manipulations of finite state machines.

[BibT_eX]

[DOI]

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

A Unified Framework for the Formal Verification of Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Formal boolean manipulations for the verification of sequential machines.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference, 1990

Verifying Temporal Properties of Sequential Machines Without Building their State Diagrams.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

1989

Automating the diagnosis and the rectification of design errors with PRIAM.

[BibT_eX]

[DOI]

Jean-Paul Billon

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Verification of Synchronous Sequential Machines Based on Symbolic Execution.

[BibT_eX]

[DOI]