Olivier Caty
According to our database1,
Olivier Caty
authored at least 6 papers
between 2003 and 2020.
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Bibliography
2020
Fundam. Informaticae, 2020
2009
Using transition test to understand timing behavior of logic circuits on UltraSPARC<sup>TM</sup> T2 family.
Proceedings of the 2009 IEEE International Test Conference, 2009
2008
Proceedings of the 2008 IEEE International Test Conference, 2008
2005
Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
2003
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003