Oliver Schliebusch

According to our database, Oliver Schliebusch authored at least 13 papers between 2001 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

Optimized ASIP synthesis from architecture description language models.

Oliver Schliebusch, Heinrich Meyr, Rainer Leupers

Kluwer, ISBN: 978-1-4020-5685-7, 2007

2006

ASIP design and synthesis for non linear filtering in image processing.

Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Automatic ADL-based operand isolation for embedded processors.

Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Optimization Techniques for ADL-Driven RTL Processor Synthesis.

Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation.

Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.

Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A universal technique for fast and flexible instruction-set architecture simulation.

Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

RTL Processor Synthesis for Architecture Exploration and Implementation.

Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl

Proceedings of the 2004 Design, 2004

2003

Processor/Memory Co-Exploration on Multiple Abstraction Levels.

Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl

Proceedings of the 2003 Design, 2003

Instruction encoding synthesis for architecture exploration using hierarchical processor models.

Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr

Proceedings of the 40th Design Automation Conference, 2003

2002

Architecture Implementation Using the Machine Description Language LISA.

Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language.

Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA.

Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001