Oliver Lexter July A. Jose

According to our database, Oliver Lexter July A. Jose authored at least 16 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process.

Chua-Chin Wang, Oliver Lexter July A. Jose, Li Lin, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Anela L. Salvador

Circuits Syst. Signal Process., June, 2024

A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array.

Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Pradyumna Vellanki

Integr., 2024

A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process.

Soumika Majumder, Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process.

Oliver Lexter July A. Jose, Yun-Che Chang, Venkata Naveen Kolakaluri, Celso B. Co, Mitch Ming-Chi Chou, Chua-Chin Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process.

Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang

IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.

Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang

Integr., May, 2023

A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder.

Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee

Circuits Syst. Signal Process., April, 2023

A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process.

Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose

IET Circuits Devices Syst., March, 2023

A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder.

Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

SiC MOSFET High Side Gate Driver Design Using HV CMOS Process.

Oliver Lexter July A. Jose, Jui-Min Kuo, Venkata Naveen Kolakaluri, Chua-Chin Wang

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle.

Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs.

Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Jui-Min Kuo, Mitch Ming-Chi Chou, Chua-Chin Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic.

Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang

Proceedings of the International Conference on IC Design and Technology, 2022

A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module.

Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Chua-Chin Wang

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS.

Chua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee

Microelectron. J., 2021