Oliver F. Haberl

According to our database, Oliver F. Haberl authored at least 7 papers between 1990 and 1995.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1995

HIST: A hierarchical self test methodology for chips, boards, and systems.

Oliver F. Haberl, Thomas Kropf

J. Electron. Test., 1995

1994

Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface.

Oliver F. Haberl, Thomas Kropf

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Eine Methode zur automatischen Synthese hierarchisch selbsttestbarer Systeme.

Oliver F. Haberl

PhD thesis, 1993

1992

A methodology for the insertion of a hierarchical and boundary-scan compatible self test.

Oliver F. Haberl, Thomas Kropf

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test.

Oliver F. Haberl, Thomas Kropf

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A chip solution to hierarchical and boundary-scan compatible board level BIST.

Oliver F. Haberl, Thomas Kropf

Proceedings of the Second Great Lakes Symposium on VLSI, 1992

1990

Generating pseudo-exhaustive vectors for external testing.

Sybille Hellebrand, Hans-Joachim Wunderlich, Oliver F. Haberl

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990