Olga Krestinskaya
Orcid: 0000-0001-8038-4558
According to our database1,
Olga Krestinskaya
authored at least 36 papers
between 2015 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2023
Towards Efficient In-memory Computing Hardware for Quantized Neural Networks: State-of-the-art, Open Challenges and Perspectives.
CoRR, 2023
2022
Towards Efficient RRAM-based Quantized Neural Networks Hardware: State-of-the-art and Open Issues.
CoRR, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2020
IEEE Trans. Neural Networks Learn. Syst., 2020
IEEE Trans. Biomed. Circuits Syst., 2020
Recursive Threshold Logic - A Bioinspired Reconfigurable Dynamic Logic System With Crossbar Arrays.
IEEE Trans. Biomed. Circuits Syst., 2020
AM-DCGAN: Analog Memristive Hardware Accelerator for Deep Convolutional Generative Adversarial Networks.
CoRR, 2020
Towards Hardware Optimal Neural Network Selection with Multi-Objective Genetic Search.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Memristive Non-Idealities: Is there any Practical Implications for Designing Neural Network Chips?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
AMSNet: Analog Memristive System Architecture for Mean-Pooling with Dropout Convolutional Neural Network.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
IEEE Trans. Emerg. Top. Comput. Intell., 2018
Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
J. Intell. Fuzzy Syst., 2018
Binary Weighted Memristive Analog Deep Neural Network for Near-Sensor Edge Processing.
CoRR, 2018
Feature extraction without learning in an analog Spatial Pooler memristive-CMOS circuit design of Hierarchical Temporal Memory.
CoRR, 2018
Bit-Plane Extracted Moving-Object Detection Using Memristive Crossbar-CAM Arrays for Edge Computing Image Devices.
IEEE Access, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Real-Time Analog Pixel-to-Pixel Dynamic Frame Differencing with Memristive Sensing Circuits.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018
Proceedings of the 2018 International Conference on Advances in Computing, 2018
Proceedings of the 2018 International Conference on Advances in Computing, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
Proceedings of the 2016 International Conference on Advances in Computing, 2016
2015
Proceedings of the 2015 International Conference on Advances in Computing, 2015