Oleg Garitselov

According to our database1, Oleg Garitselov authored at least 11 papers between 2011 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2012
Accurate Polynomial Metamodeling-Based Ultra-Fast Bee Colony Optimization of a Nano-CMOS Phase-Locked Loop.
J. Low Power Electron., 2012

Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier.
Proceedings of the 25th International Conference on VLSI Design, 2012

Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization.
Proceedings of the 25th International Conference on VLSI Design, 2012

Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Polynomial-metamodel assisted fast power optimization of Nano-CMOS PLL components.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

2011
Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Parabilis: Speeding up Single-Threaded Applications by Extracting Fine-Grained Threads for Multi-core Execution.
Proceedings of the 10th International Symposium on Parallel and Distributed Computing, 2011

Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL.
Proceedings of the International Symposium on Electronic System Design, 2011


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