Oguz Ergin
Orcid: 0000-0003-2701-3787
According to our database1,
Oguz Ergin
authored at least 85 papers
between 2002 and 2024.
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Bibliography
2024
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture.
ACM Trans. Archit. Code Optim., September, 2024
Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance.
CoRR, 2024
Leveraging Adversarial Detection to Enable Scalable and Low Overhead RowHammer Mitigations.
CoRR, 2024
BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
2023
DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
ACM Trans. Archit. Code Optim., March, 2023
Proceedings of the IEEE European Test Symposium, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Micro, 2022
CoRR, 2022
Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture.
CoRR, 2022
Proceedings of the 31st USENIX Security Symposium, 2022
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022
2021
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2020
2019
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019
2018
Microelectron. Reliab., 2018
CoRR, 2018
CoRR, 2018
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies.
BMC Genom., 2018
2017
GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping.
Bioinform., 2017
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2016
URFA-Update based register file architecture with partial register write for energy efficiency.
Microprocess. Microsystems, 2016
GateKeeper: Enabling Fast Pre-Alignment in DNA Short Read Mapping with a New Streaming Accelerator Architecture.
CoRR, 2016
IEEE Comput. Archit. Lett., 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
ACM Trans. Archit. Code Optim., 2014
Exploiting processor features to implement error detection in reduced precision matrix multiplications.
Microprocess. Microsystems, 2014
Microprocess. Microsystems, 2014
IEEE Comput. Archit. Lett., 2014
Proceedings of the VISAPP 2014, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
2013
IEEE Comput. Archit. Lett., 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In Comparators.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Tag simplification: Achieving power efficiency through reducing the complexity of the wakeup logic.
Proceedings of the International Conference on Energy Aware Computing, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
2010
Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands.
J. Circuits Syst. Comput., 2010
Dynamic register file partitioning in superscalar microprocessors for energy efficiency.
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the Architecture of Computing Systems, 2010
Proceedings of the Architecture of Computing Systems, 2010
2009
IEEE Trans. Dependable Secur. Comput., 2009
ACM Trans. Archit. Code Optim., 2009
ACM Trans. Archit. Code Optim., 2009
J. Circuits Syst. Comput., 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
2007
IEEE Comput. Archit. Lett., 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
2006
IEEE Trans. Computers, 2006
ACM Trans. Archit. Code Optim., 2006
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005
2004
IEEE Trans. Computers, 2004
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization.
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003
2002
A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002