Oguz Ergin

Orcid: 0000-0003-2701-3787

According to our database1, Oguz Ergin authored at least 85 papers between 2002 and 2024.

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Bibliography

2024
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture.
ACM Trans. Archit. Code Optim., September, 2024

Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance.
CoRR, 2024

Leveraging Adversarial Detection to Enable Scalable and Low Overhead RowHammer Mitigations.
CoRR, 2024

BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023
DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM.
ACM Trans. Archit. Code Optim., March, 2023

DEV-PIM: Dynamic Execution Validation with Processing-in-Memory.
Proceedings of the IEEE European Test Symposium, 2023

2022
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches.
IEEE Trans. Very Large Scale Integr. Syst., 2022

MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Can We Trust Undervolting in FPGA-Based Deep Learning Designs at Harsh Conditions?
IEEE Micro, 2022

TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs.
CoRR, 2022

Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture.
CoRR, 2022

Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks.
Proceedings of the 31st USENIX Security Symposium, 2022

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

ERIC: An Efficient and Practical Software Obfuscation Framework.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

2021
MoRS: An Approximate Fault Modelling Framework for Reduced-Voltage SRAMs.
CoRR, 2021

QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
A Microprocessor Protection Architecture against Hardware Trojans in Memories.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2020

2019
A Novel FPGA-Based High Throughput Accelerator For Binary Search Trees.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

2018
Opcode vector: An efficient scheme to detect soft errors in instructions.
Microelectron. Reliab., 2018

Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency.
CoRR, 2018

SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure.
CoRR, 2018

GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies.
BMC Genom., 2018

2017
GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping.
Bioinform., 2017

SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Detecting errors in instructions with bloom filters.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
URFA-Update based register file architecture with partial register write for energy efficiency.
Microprocess. Microsystems, 2016

GateKeeper: Enabling Fast Pre-Alignment in DNA Short Read Mapping with a New Streaming Accelerator Architecture.
CoRR, 2016

Exploiting Existing Copies in Register File for Soft Error Correction.
IEEE Comput. Archit. Lett., 2016

ChargeCache: Reducing DRAM latency by exploiting row access locality.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Error recovery through partial value similarity.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015
Using value similarity of registers for soft error mitigation.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

User-specific skin temperature-aware DVFS for smartphones.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection.
ACM Trans. Archit. Code Optim., 2014

Exploiting processor features to implement error detection in reduced precision matrix multiplications.
Microprocess. Microsystems, 2014

Bit Impact Factor: Towards making fair vulnerability comparison.
Microprocess. Microsystems, 2014

Exploiting Virtual Addressing for Increasing Reliability.
IEEE Comput. Archit. Lett., 2014

GPU based Parallel Image Processing Library for Embedded Systems.
Proceedings of the VISAPP 2014, 2014

Exploiting a fast and simple ECC for scaling supply voltage in level-1 caches.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013
Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values.
IEEE Comput. Archit. Lett., 2013

Adapting the columns of storage components for lower static energy dissipation.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Exploiting replicated checkpoints for soft error detection and correction.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In Comparators.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Tag simplification: Achieving power efficiency through reducing the complexity of the wakeup logic.
Proceedings of the International Conference on Energy Aware Computing, 2011

Using content-aware bitcells to reduce static energy dissipation.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands.
J. Circuits Syst. Comput., 2010

Dynamic register file partitioning in superscalar microprocessors for energy efficiency.
Proceedings of the 28th International Conference on Computer Design, 2010

Exploiting Inactive Rename Slots for Detecting Soft Errors.
Proceedings of the Architecture of Computing Systems, 2010

Complexity-Effective Rename Table Design for Rapid Speculation Recovery.
Proceedings of the Architecture of Computing Systems, 2010

2009
Reducing Soft Errors through Operand Width Aware Policies.
IEEE Trans. Dependable Secur. Comput., 2009

Energy-efficient register caching with compiler assistance.
ACM Trans. Archit. Code Optim., 2009

Exploring the limits of early register release: Exploiting compiler analysis.
ACM Trans. Archit. Code Optim., 2009

Modifying the Data-Holding Components of the Microprocessors for Energy Efficiency.
J. Circuits Syst. Comput., 2009

Reducing parity generation latency through input value aware circuits.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
Refueling: Preventing Wire Degradation due to Electromigration.
IEEE Micro, 2008

2007
Using Tag-Match Comparators for Detecting Soft Errors.
IEEE Comput. Archit. Lett., 2007

Fuse: A Technique to Anticipate Failures due to Degradation in ALUs.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
Early Register Deallocation Mechanisms Using Checkpointed Register Files.
IEEE Trans. Computers, 2006

Instruction packing: Toward fast and energy-efficient instruction scheduling.
ACM Trans. Archit. Code Optim., 2006

Impact of Parameter Variations on Circuits and Microarchitecture.
IEEE Micro, 2006

Exploiting Narrow Values for Soft Error Tolerance.
IEEE Comput. Archit. Lett., 2006

Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Empowering a helper cluster through data-width aware instruction selection policies.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005
Instruction packing: reducing power and delay of the dynamic scheduling logic.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Power-Efficient Wakeup Tag Broadcast.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Compiler Directed Early Register Release.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004
Energy Efficient Comparators for Superscalar Datapaths.
IEEE Trans. Computers, 2004

Isolating Short-Lived Operands for Energy Reduction.
IEEE Trans. Computers, 2004

Complexity-Effective Reorder Buffer Designs for Superscalar Processors.
IEEE Trans. Computers, 2004

Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization.
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Increasing Processor Performance Through Early Register Release.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Defining Wakeup Width for Efficient Dynamic Scheduling.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Energy-efficient issue queue design.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Energy Efficient Register Renaming.
Proceedings of the Integrated Circuit and System Design, 2003

Power efficient comparators for long arguments in superscalar processors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Reducing reorder buffer complexity through selective operand caching.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Distributed Reorder Buffer Schemes for Low Power.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Reducing Datapath Energy through the Isolation of Short-Lived Operands.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002
A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002


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