Odysseas Zografos

According to our database, Odysseas Zografos authored at least 24 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits.

Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, Shashank Ekbote, Nick Stevens-Yu, David Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5).

S. Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, Gioele Mirabelli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation.

Subrat Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, A. Sharma, G. Mirabeli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert

Proceedings of the IEEE International Reliability Physics Symposium, 2024

GNN-assisted Back-side Clock Routing Methodology for Advance Technologies.

Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.

Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs).

Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert

Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era.

Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert

IEEE Trans. Very Large Scale Integr. Syst., 2022

Challenges and targets of MRAM-enabled scaled spintronic logic circuits.

Fanfan Meng, Florin Ciubotaru, S.-Y. Lee, Odysseas Zografos, M. Gupta, V. D. Nguyen, Sebastien Couet, Gouri Sankar Kar, Giovanni De Micheli, Christoph Adelmann, I. Asselberghs

CoRR, 2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.

Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper.

Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne

Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022

System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents.

Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Kristof Croes, Mustafa Badaroglu

Proceedings of the IEEE International Reliability Physics Symposium, 2022

Design enablement of CFET devices for sub-2nm CMOS nodes.

Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network.

Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Mustafa Badaroglu, Kristof Croes

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm.

Subrat Mishra, Pieter Weckx, Odysseas Zografos, Ji-Yung Lin, Alessio Spessot, Francky Catthoor

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper).

Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2018

Majority logic synthesis.

Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies.

Eleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini, Rudy Lauwereins, Giovanni De Micheli

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Wave pipelining for majority-based beyond-CMOS technologies.

Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Non-volatile spin wave majority gate at the nanoscale.

Odysseas Zografos, Sourav Dutta, Mauricio Manfrini, Adrien Vaysset, Bart Sorée, Azad Naeemi, Praveen Raghavan, Rudy Lauwereins, Iuliana P. Radu

CoRR, 2016

Inversion optimization in Majority-Inverter Graphs.

Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

2015

Area and routing efficiency of SWD circuits compared to advanced CMOS.

Odysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubotaru, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Aaron Thean

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

System-level assessment and area evaluation of Spin Wave logic circuits.

Odysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Diederik Verkest, Aaron Thean

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Novel grid-based power routing scheme for regular controllable-polarity FET arrangements.

Odysseas Zografos, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Majority Logic Synthesis for Spin Wave Technology.

Odysseas Zografos, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014